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/*
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 * Defining registers address and its bit definitions of MAX77620 and MAX20024
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 *
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 * Copyright (c) 2019-2020 CTCaer
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2, as published by the Free Software Foundation.
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 */
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#ifndef _MFD_MAX77620_H_
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#define _MFD_MAX77620_H_
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#define MAX77620_I2C_ADDR 0x3C
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/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
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#define MAX77620_REG_CNFGGLBL1      0x00
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#define  MAX77620_CNFGGLBL1_LBRSTEN           BIT(0)
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#define  MAX77620_CNFGGLBL1_LBDAC_MASK        0x0E
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#define  MAX77620_CNFGGLBL1_LBDAC_2700        (0 << 1)
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#define  MAX77620_CNFGGLBL1_LBDAC_2800        (1 << 1)
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#define  MAX77620_CNFGGLBL1_LBDAC_2900        (2 << 1)
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#define  MAX77620_CNFGGLBL1_LBDAC_3000        (3 << 1)
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#define  MAX77620_CNFGGLBL1_LBDAC_3100        (4 << 1)
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#define  MAX77620_CNFGGLBL1_LBDAC_3200        (5 << 1)
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#define  MAX77620_CNFGGLBL1_LBDAC_3300        (6 << 1)
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#define  MAX77620_CNFGGLBL1_LBDAC_3400        (7 << 1)
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#define  MAX77620_CNFGGLBL1_LBHYST_100        (0 << 4)
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#define  MAX77620_CNFGGLBL1_LBHYST_200        (1 << 4)
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#define  MAX77620_CNFGGLBL1_LBHYST_300        (2 << 4)
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#define  MAX77620_CNFGGLBL1_LBHYST_400        (3 << 4)
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#define  MAX77620_CNFGGLBL1_MPPLD             BIT(6)
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#define  MAX77620_CNFGGLBL1_LBDAC_EN          BIT(7)
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#define MAX77620_REG_CNFGGLBL2      0x01
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#define  MAX77620_TWD_MASK                    0x3
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#define  MAX77620_TWD_2s                      0x0
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#define  MAX77620_TWD_16s                     0x1
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#define  MAX77620_TWD_64s                     0x2
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#define  MAX77620_TWD_128s                    0x3
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#define  MAX77620_WDTEN                       BIT(2)
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#define  MAX77620_WDTSLPC                     BIT(3)
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#define  MAX77620_WDTOFFC                     BIT(4)
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#define  MAX77620_GLBL_LPM                    BIT(5)
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#define  MAX77620_I2CTWD_MASK                 0xC0
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#define  MAX77620_I2CTWD_DISABLED             0x00
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#define  MAX77620_I2CTWD_1_33ms               0x40
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#define  MAX77620_I2CTWD_35_7ms               0x80
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#define  MAX77620_I2CTWD_41_7ms               0xC0
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#define MAX77620_REG_CNFGGLBL3      0x02
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#define  MAX77620_WDTC_MASK                   0x3
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#define MAX77620_REG_CNFG1_32K      0x03
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#define  MAX77620_CNFG1_PWR_MD_32K_MASK       0x3
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#define  MAX77620_CNFG1_32K_OUT0_EN           BIT(2)
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#define  MAX77620_CNFG1_32KLOAD_MASK          0x30
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#define  MAX77620_CNFG1_32K_OK                BIT(7)
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#define MAX77620_REG_CNFGBBC        0x04
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#define  MAX77620_CNFGBBC_ENABLE              BIT(0)
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#define  MAX77620_CNFGBBC_CURRENT_MASK        0x06
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#define  MAX77620_CNFGBBC_CURRENT_SHIFT       1
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#define  MAX77620_CNFGBBC_VOLTAGE_MASK        0x18
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#define  MAX77620_CNFGBBC_VOLTAGE_SHIFT       3
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#define  MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
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#define  MAX77620_CNFGBBC_RESISTOR_MASK       0xC0
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#define  MAX77620_CNFGBBC_RESISTOR_SHIFT      6
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#define  MAX77620_CNFGBBC_RESISTOR_100        (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define  MAX77620_CNFGBBC_RESISTOR_1K         (1 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define  MAX77620_CNFGBBC_RESISTOR_3K         (2 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define  MAX77620_CNFGBBC_RESISTOR_6K         (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
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#define MAX77620_REG_IRQTOP         0x05
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#define MAX77620_REG_IRQTOPM        0x0D
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#define  MAX77620_IRQ_TOP_ONOFF_MASK          BIT(1)
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#define  MAX77620_IRQ_TOP_32K_MASK            BIT(2)
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#define  MAX77620_IRQ_TOP_RTC_MASK            BIT(3)
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#define  MAX77620_IRQ_TOP_GPIO_MASK           BIT(4)
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#define  MAX77620_IRQ_TOP_LDO_MASK            BIT(5)
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#define  MAX77620_IRQ_TOP_SD_MASK             BIT(6)
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#define  MAX77620_IRQ_TOP_GLBL_MASK           BIT(7)
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#define MAX77620_REG_INTLBT         0x06
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#define MAX77620_REG_INTENLBT       0x0E
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#define  MAX77620_IRQ_GLBLM_MASK              BIT(0)
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#define  MAX77620_IRQ_TJALRM2_MASK            BIT(1)
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#define  MAX77620_IRQ_TJALRM1_MASK            BIT(2)
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#define  MAX77620_IRQ_LBM_MASK                BIT(3)
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#define MAX77620_REG_IRQSD          0x07
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#define MAX77620_REG_IRQMASKSD      0x0F
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#define  MAX77620_IRQSD_PFI_SD3               BIT(4)
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#define  MAX77620_IRQSD_PFI_SD2               BIT(5)
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#define  MAX77620_IRQSD_PFI_SD1               BIT(6)
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#define  MAX77620_IRQSD_PFI_SD0               BIT(7)
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#define MAX77620_REG_IRQ_LVL2_L0_7  0x08 // LDO number that irq occurred.
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#define MAX77620_REG_IRQ_MSK_L0_7   0x10
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#define MAX77620_REG_IRQ_LVL2_L8    0x09 // LDO number that irq occurred. Only bit0: LDO8 is valid.
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#define MAX77620_REG_IRQ_MSK_L8     0x11
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#define MAX77620_REG_IRQ_LVL2_GPIO  0x0A // Edge detection interrupt.
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#define MAX77620_REG_ONOFFIRQ       0x0B
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#define MAX77620_REG_ONOFFIRQM      0x12
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#define  MAX77620_ONOFFIRQ_MRWRN              BIT(0)
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#define  MAX77620_ONOFFIRQ_EN0_1SEC           BIT(1)
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#define  MAX77620_ONOFFIRQ_EN0_F              BIT(2)
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#define  MAX77620_ONOFFIRQ_EN0_R              BIT(3)
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#define  MAX77620_ONOFFIRQ_LID_F              BIT(4)
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#define  MAX77620_ONOFFIRQ_LID_R              BIT(5)
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#define  MAX77620_ONOFFIRQ_ACOK_F             BIT(6)
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#define  MAX77620_ONOFFIRQ_ACOK_R             BIT(7)
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#define MAX77620_REG_NVERC          0x0C // Shutdown reason (non-volatile).
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#define  MAX77620_NVERC_SHDN                  BIT(0)
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#define  MAX77620_NVERC_WTCHDG                BIT(1)
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#define  MAX77620_NVERC_HDRST                 BIT(2)
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#define  MAX77620_NVERC_TOVLD                 BIT(3)
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#define  MAX77620_NVERC_MBLSD                 BIT(4)
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#define  MAX77620_NVERC_MBO                   BIT(5)
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#define  MAX77620_NVERC_MBU                   BIT(6)
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#define  MAX77620_NVERC_RSTIN                 BIT(7)
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#define MAX77620_REG_STATLBT        0x13
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#define MAX77620_REG_STATSD         0x14
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#define MAX77620_REG_ONOFFSTAT      0x15
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#define  MAX77620_ONOFFSTAT_LID     BIT(0)
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#define  MAX77620_ONOFFSTAT_ACOK    BIT(1)
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#define  MAX77620_ONOFFSTAT_EN0     BIT(2)
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/* SD and LDO Registers */
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#define MAX77620_REG_SD0            0x16
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#define MAX77620_REG_SD1            0x17
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#define MAX77620_REG_SD2            0x18
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#define MAX77620_REG_SD3            0x19
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#define MAX77620_REG_SD4            0x1A
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#define MAX77620_REG_DVSSD0         0x1B
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#define MAX77620_REG_DVSSD1         0x1C
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#define  MAX77620_SDX_VOLT_MASK               0xFF
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#define  MAX77620_SD0_VOLT_MASK               0x7F // Max is 0x40.
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#define  MAX77620_SD1_VOLT_MASK               0x7F // Max is 0x4C.
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#define  MAX77620_LDO_VOLT_MASK               0x3F
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#define MAX77620_REG_SD0_CFG        0x1D
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#define MAX77620_REG_SD1_CFG        0x1E
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#define MAX77620_REG_SD2_CFG        0x1F
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#define MAX77620_REG_SD3_CFG        0x20
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#define MAX77620_REG_SD4_CFG        0x21
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#define  MAX77620_SD_SR_MASK                  0xC0
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#define  MAX77620_SD_SR_SHIFT                 6
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#define  MAX77620_SD_POWER_MODE_MASK          0x30
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#define  MAX77620_SD_POWER_MODE_SHIFT         4
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#define  MAX77620_SD_CFG1_ADE_MASK            BIT(3)
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#define  MAX77620_SD_CFG1_ADE_DISABLE         0
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#define  MAX77620_SD_CFG1_ADE_ENABLE          BIT(3)
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#define  MAX77620_SD_FPWM_MASK                0x04
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#define  MAX77620_SD_FPWM_SHIFT               2
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#define  MAX77620_SD_FSRADE_MASK              0x01
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#define  MAX77620_SD_FSRADE_SHIFT             0
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#define  MAX77620_SD_CFG1_FPWM_SD_MASK        BIT(2)
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#define  MAX77620_SD_CFG1_FPWM_SD_SKIP        0
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#define  MAX77620_SD_CFG1_FPWM_SD_FPWM        BIT(2)
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#define  MAX77620_SD_CFG1_MPOK_MASK           BIT(1)
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#define  MAX77620_SD_CFG1_FSRADE_SD_MASK      BIT(0)
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#define  MAX77620_SD_CFG1_FSRADE_SD_DISABLE   0
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#define  MAX77620_SD_CFG1_FSRADE_SD_ENABLE    BIT(0)
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#define MAX77620_REG_SD_CFG2        0x22
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#define  MAX77620_SD_CNF2_RSVD                BIT(0)
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#define  MAX77620_SD_CNF2_ROVS_EN_SD1         BIT(1)
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#define  MAX77620_SD_CNF2_ROVS_EN_SD0         BIT(2)
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#define MAX77620_REG_LDO0_CFG       0x23
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#define MAX77620_REG_LDO0_CFG2      0x24
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#define MAX77620_REG_LDO1_CFG       0x25
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#define MAX77620_REG_LDO1_CFG2      0x26
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#define MAX77620_REG_LDO2_CFG       0x27
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#define MAX77620_REG_LDO2_CFG2      0x28
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#define MAX77620_REG_LDO3_CFG       0x29
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#define MAX77620_REG_LDO3_CFG2      0x2A
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#define MAX77620_REG_LDO4_CFG       0x2B
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#define MAX77620_REG_LDO4_CFG2      0x2C
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#define MAX77620_REG_LDO5_CFG       0x2D
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#define MAX77620_REG_LDO5_CFG2      0x2E
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#define MAX77620_REG_LDO6_CFG       0x2F
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#define MAX77620_REG_LDO6_CFG2      0x30
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#define MAX77620_REG_LDO7_CFG       0x31
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#define MAX77620_REG_LDO7_CFG2      0x32
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#define MAX77620_REG_LDO8_CFG       0x33
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#define MAX77620_REG_LDO8_CFG2      0x34
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/*! LDO CFG */
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#define  MAX77620_LDO_POWER_MODE_SHIFT        6
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#define  MAX77620_LDO_POWER_MODE_MASK         (3 << MAX77620_LDO_POWER_MODE_SHIFT)
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#define  MAX77620_POWER_MODE_NORMAL	          3
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#define  MAX77620_POWER_MODE_LPM              2
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#define  MAX77620_POWER_MODE_GLPM             1
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#define  MAX77620_POWER_MODE_DISABLE          0
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/*! LDO CFG2 */
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#define  MAX77620_LDO_CFG2_SS_MASK            (1 << 0)
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#define  MAX77620_LDO_CFG2_SS_FAST            (0 << 0)
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#define  MAX77620_LDO_CFG2_SS_SLOW            (1 << 0)
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#define  MAX77620_LDO_CFG2_ADE_MASK           (1 << 1)
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#define  MAX77620_LDO_CFG2_ADE_DISABLE        (0 << 1)
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#define  MAX77620_LDO_CFG2_ADE_ENABLE         (1 << 1)
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#define  MAX77620_LDO_CFG2_MPOK_MASK          BIT(2)
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#define  MAX77620_LDO_CFG2_POK_MASK           BIT(3)
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#define  MAX77620_LDO_CFG2_COMP_SHIFT         4
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#define  MAX77620_LDO_CFG2_COMP_MASK          (3 << MAX77620_LDO_COMP_SHIFT)
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#define  MAX77620_LDO_CFG2_COMP_SLOW 	      3
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#define  MAX77620_LDO_CFG2_COMP_MID_SLOW      2
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#define  MAX77620_LDO_CFG2_COMP_MID_FAST      1
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#define  MAX77620_LDO_CFG2_COMP_FAST          0
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#define  MAX77620_LDO_CFG2_ALPM_EN_MASK       BIT(6)
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#define  MAX77620_LDO_CFG2_OVCLMP_MASK        BIT(7)
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#define MAX77620_REG_LDO_CFG3       0x35
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#define  MAX77620_LDO_BIAS_EN                 BIT(0)
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#define  MAX77620_TRACK4_SHIFT                5
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#define  MAX77620_TRACK4_MASK                 (1 << MAX77620_TRACK4_SHIFT)
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#define MAX77620_REG_GPIO0          0x36
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#define MAX77620_REG_GPIO1          0x37
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#define MAX77620_REG_GPIO2          0x38
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#define MAX77620_REG_GPIO3          0x39
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#define MAX77620_REG_GPIO4          0x3A
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#define MAX77620_REG_GPIO5          0x3B
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#define MAX77620_REG_GPIO6          0x3C
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#define MAX77620_REG_GPIO7          0x3D
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#define  MAX77620_CNFG_GPIO_DRV_MASK          (1 << 0)
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#define  MAX77620_CNFG_GPIO_DRV_PUSHPULL      (1 << 0)
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#define  MAX77620_CNFG_GPIO_DRV_OPENDRAIN     (0 << 0)
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#define  MAX77620_CNFG_GPIO_DIR_MASK          (1 << 1)
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#define  MAX77620_CNFG_GPIO_DIR_INPUT         (1 << 1)
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#define  MAX77620_CNFG_GPIO_DIR_OUTPUT        (0 << 1)
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#define  MAX77620_CNFG_GPIO_INPUT_VAL_MASK    (1 << 2)
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#define  MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK   (1 << 3)
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#define  MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH   (1 << 3)
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#define  MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW    (0 << 3)
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#define  MAX77620_CNFG_GPIO_INT_MASK          (0x3 << 4)
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#define  MAX77620_CNFG_GPIO_INT_FALLING       (1 << 4)
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#define  MAX77620_CNFG_GPIO_INT_RISING        (1 << 5)
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#define  MAX77620_CNFG_GPIO_DBNC_MASK         (0x3 << 6)
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#define  MAX77620_CNFG_GPIO_DBNC_None         (0x0 << 6)
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#define  MAX77620_CNFG_GPIO_DBNC_8ms          (0x1 << 6)
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#define  MAX77620_CNFG_GPIO_DBNC_16ms         (0x2 << 6)
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#define  MAX77620_CNFG_GPIO_DBNC_32ms         (0x3 << 6)
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#define  MAX77620_GPIO_OUTPUT_DISABLE         0
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#define  MAX77620_GPIO_OUTPUT_ENABLE          1
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#define MAX77620_REG_PUE_GPIO       0x3E // Gpio Pullup resistor enable.
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#define MAX77620_REG_PDE_GPIO       0x3F // Gpio Pulldown resistor enable.
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#define MAX77620_REG_AME_GPIO       0x40 // Gpio pinmuxing. Clear bits are Standard GPIO.
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#define MAX77620_REG_ONOFFCNFG1     0x41
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#define  MAX20024_ONOFFCNFG1_CLRSE            0x18
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#define  MAX77620_ONOFFCNFG1_PWR_OFF          BIT(1)
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#define  MAX77620_ONOFFCNFG1_SLPEN            BIT(2)
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#define  MAX77620_ONOFFCNFG1_MRT_SHIFT        0x3
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#define  MAX77620_ONOFFCNFG1_MRT_MASK         0x38
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#define  MAX77620_ONOFFCNFG1_RSVD             BIT(6)
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#define  MAX77620_ONOFFCNFG1_SFT_RST          BIT(7)
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#define MAX77620_REG_ONOFFCNFG2     0x42
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#define  MAX77620_ONOFFCNFG2_WK_EN0           BIT(0)
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#define  MAX77620_ONOFFCNFG2_WK_ALARM2        BIT(1)
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#define  MAX77620_ONOFFCNFG2_WK_ALARM1        BIT(2)
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#define  MAX77620_ONOFFCNFG2_WK_MBATT         BIT(3) // MBATT event generates a wakeup signal. use it in android/l4t?
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#define  MAX77620_ONOFFCNFG2_WK_ACOK          BIT(4)
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#define  MAX77620_ONOFFCNFG2_SLP_LPM_MSK      BIT(5)
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#define  MAX77620_ONOFFCNFG2_WD_RST_WK        BIT(6)
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#define  MAX77620_ONOFFCNFG2_SFT_RST_WK       BIT(7)
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/* FPS Registers */
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#define MAX77620_REG_FPS_CFG0       0x43 // FPS0.
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#define MAX77620_REG_FPS_CFG1       0x44 // FPS1.
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#define MAX77620_REG_FPS_CFG2       0x45 // FPS2.
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#define  MAX77620_FPS_ENFPS_SW_MASK           0x01
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#define  MAX77620_FPS_ENFPS_SW                0x01
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#define  MAX77620_FPS_EN_SRC_SHIFT            1
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#define  MAX77620_FPS_EN_SRC_MASK             0x06
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#define  MAX77620_FPS_TIME_PERIOD_SHIFT       3
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#define  MAX77620_FPS_TIME_PERIOD_MASK        0x38
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#define MAX77620_REG_FPS_LDO0       0x46
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#define MAX77620_REG_FPS_LDO1       0x47
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#define MAX77620_REG_FPS_LDO2       0x48
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#define MAX77620_REG_FPS_LDO3       0x49
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#define MAX77620_REG_FPS_LDO4       0x4A
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#define MAX77620_REG_FPS_LDO5       0x4B
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#define MAX77620_REG_FPS_LDO6       0x4C
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#define MAX77620_REG_FPS_LDO7       0x4D
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#define MAX77620_REG_FPS_LDO8       0x4E
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#define MAX77620_REG_FPS_SD0        0x4F
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#define MAX77620_REG_FPS_SD1        0x50
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#define MAX77620_REG_FPS_SD2        0x51
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#define MAX77620_REG_FPS_SD3        0x52
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#define MAX77620_REG_FPS_SD4        0x53
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#define MAX77620_REG_FPS_GPIO1      0x54
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#define MAX77620_REG_FPS_GPIO2      0x55
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#define MAX77620_REG_FPS_GPIO3      0x56
304
#define MAX77620_REG_FPS_RSO        0x57
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#define  MAX77620_FPS_PD_PERIOD_SHIFT         0
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#define  MAX77620_FPS_PD_PERIOD_MASK          0x07
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#define  MAX77620_FPS_PU_PERIOD_SHIFT         3
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#define  MAX77620_FPS_PU_PERIOD_MASK          0x38
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#define  MAX77620_FPS_SRC_SHIFT               6
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#define  MAX77620_FPS_SRC_MASK                0xC0
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#define MAX77620_FPS_COUNT 3
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#define MAX77620_FPS_PERIOD_MIN_US 40
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#define MAX77620_FPS_PERIOD_MAX_US 2560
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#define MAX77620_REG_CID0           0x58
317
#define MAX77620_REG_CID1           0x59
318
#define MAX77620_REG_CID2           0x5A
319
#define MAX77620_REG_CID3           0x5B
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#define MAX77620_REG_CID4           0x5C // OTP version.
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#define MAX77620_REG_CID5           0x5D // ES version.
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#define  MAX77620_CID_DIDO_MASK               0xF
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#define  MAX77620_CID_DIDO_SHIFT              0
324
#define  MAX77620_CID_DIDM_MASK               0xF0
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#define  MAX77620_CID_DIDM_SHIFT              4
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/* Device Identification Metal */
328
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
329
/* Device Indentification OTP */
330
#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
331

332
#define MAX77620_REG_DVSSD4         0x5E
333
#define MAX20024_REG_MAX_ADD        0x70
334

335
#define MAX77620_IRQ_LVL2_GPIO_EDGE0          BIT(0)
336
#define MAX77620_IRQ_LVL2_GPIO_EDGE1          BIT(1)
337
#define MAX77620_IRQ_LVL2_GPIO_EDGE2          BIT(2)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE3          BIT(3)
339
#define MAX77620_IRQ_LVL2_GPIO_EDGE4          BIT(4)
340
#define MAX77620_IRQ_LVL2_GPIO_EDGE5          BIT(5)
341
#define MAX77620_IRQ_LVL2_GPIO_EDGE6          BIT(6)
342
#define MAX77620_IRQ_LVL2_GPIO_EDGE7          BIT(7)
343

344
/* Interrupts */
345
enum {
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	MAX77620_IRQ_TOP_GLBL,		/* Low-Battery */
347
	MAX77620_IRQ_TOP_SD,		/* SD power fail */
348
	MAX77620_IRQ_TOP_LDO,		/* LDO power fail */
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	MAX77620_IRQ_TOP_GPIO,		/* TOP GPIO internal int to MAX77620 */
350
	MAX77620_IRQ_TOP_RTC,		/* RTC */
351
	MAX77620_IRQ_TOP_32K,		/* 32kHz oscillator */
352
	MAX77620_IRQ_TOP_ONOFF,		/* ON/OFF oscillator */
353
	MAX77620_IRQ_LBT_MBATLOW,	/* Thermal alarm status, > 120C */
354
	MAX77620_IRQ_LBT_TJALRM1,	/* Thermal alarm status, > 120C */
355
	MAX77620_IRQ_LBT_TJALRM2,	/* Thermal alarm status, > 140C */
356
};
357

358
/* GPIOs */
359
enum {
360
	MAX77620_GPIO0,
361
	MAX77620_GPIO1,
362
	MAX77620_GPIO2,
363
	MAX77620_GPIO3,
364
	MAX77620_GPIO4,
365
	MAX77620_GPIO5,
366
	MAX77620_GPIO6,
367
	MAX77620_GPIO7,
368
	MAX77620_GPIO_NR,
369
};
370

371
/* FPS Source */
372
enum max77620_fps_src {
373
	MAX77620_FPS_SRC_0,
374
	MAX77620_FPS_SRC_1,
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	MAX77620_FPS_SRC_2,
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	MAX77620_FPS_SRC_NONE,
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	MAX77620_FPS_SRC_DEF,
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};
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#endif /* _MFD_MAX77620_H_ */
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