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/*
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 * Copyright (c) 2020 CTCaer
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef _MAX77812_H_
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#define _MAX77812_H_
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#define MAX77812_PHASE31_CPU_I2C_ADDR  0x31 // High power GPU. 2 Outputs: 3-phase M1 + 1-phase M4.
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#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // Low  power GPU. 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
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#define MAX77812_REG_RSET			0x00
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#define MAX77812_REG_INT_SRC		0x01
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#define MAX77812_REG_INT_SRC_M		0x02
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#define MAX77812_REG_TOPSYS_INT		0x03
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#define MAX77812_REG_TOPSYS_INT_M	0x04
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#define MAX77812_REG_TOPSYS_STAT	0x05
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#define MAX77812_REG_EN_CTRL		0x06
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#define  MAX77812_EN_CTRL_ENABLE      1
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#define  MAX77812_EN_CTRL_EN_M1_SHIFT 0
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#define  MAX77812_EN_CTRL_EN_M1_MASK  (1 << MAX77812_EN_CTRL_EN_M1_SHIFT)
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#define  MAX77812_EN_CTRL_EN_M2_SHIFT 2
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#define  MAX77812_EN_CTRL_EN_M2_MASK  (1 << MAX77812_EN_CTRL_EN_M2_SHIFT)
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#define  MAX77812_EN_CTRL_EN_M3_SHIFT 4
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#define  MAX77812_EN_CTRL_EN_M3_MASK  (1 << MAX77812_EN_CTRL_EN_M3_SHIFT)
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#define  MAX77812_EN_CTRL_EN_M4_SHIFT 6
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#define  MAX77812_EN_CTRL_EN_M4_MASK  (1 << MAX77812_EN_CTRL_EN_M4_SHIFT)
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#define MAX77812_REG_STUP_DLY2		0x07
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#define MAX77812_REG_STUP_DLY3		0x08
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#define MAX77812_REG_STUP_DLY4		0x09
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#define MAX77812_REG_SHDN_DLY1		0x0A
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#define MAX77812_REG_SHDN_DLY2		0x0B
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#define MAX77812_REG_SHDN_DLY3		0x0C
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#define MAX77812_REG_SHDN_DLY4		0x0D
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#define MAX77812_REG_WDTRSTB_DEB	0x0E
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#define MAX77812_REG_GPI_FUNC		0x0F
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#define MAX77812_REG_GPI_DEB1		0x10
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#define MAX77812_REG_GPI_DEB2		0x11
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#define MAX77812_REG_GPI_PD_CTRL	0x12
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#define MAX77812_REG_PROT_CFG		0x13
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#define MAX77812_REG_VERSION		0x14
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#define MAX77812_REG_I2C_CFG		0x15
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#define MAX77812_REG_BUCK_INT		0x20
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#define MAX77812_REG_BUCK_INT_M		0x21
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#define MAX77812_REG_BUCK_STAT		0x22
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#define MAX77812_REG_M1_VOUT		0x23 // GPU.
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#define MAX77812_REG_M2_VOUT		0x24
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#define MAX77812_REG_M3_VOUT		0x25 // DRAM on PHASE211.
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#define MAX77812_REG_M4_VOUT		0x26 // CPU.
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#define MAX77812_REG_M1_VOUT_D		0x27
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#define MAX77812_REG_M2_VOUT_D		0x28
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#define MAX77812_REG_M3_VOUT_D		0x29
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#define MAX77812_REG_M4_VOUT_D		0x2A
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#define MAX77812_REG_M1_VOUT_S		0x2B
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#define MAX77812_REG_M2_VOUT_S		0x2C
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#define MAX77812_REG_M3_VOUT_S		0x2D
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#define MAX77812_REG_M4_VOUT_S		0x2E
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#define MAX77812_REG_M1_CFG			0x2F // HOS: M1_ILIM - 7.2A/4.8A.
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#define MAX77812_REG_M2_CFG			0x30 // HOS: M2_ILIM - 7.2A/4.8A.
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#define MAX77812_REG_M3_CFG			0x31 // HOS: M3_ILIM - 7.2A/4.8A.
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#define MAX77812_REG_M4_CFG			0x32 // HOS: M4_ILIM - 7.2A/4.8A.
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#define MAX77812_REG_GLB_CFG1		0x33 // HOS: B_SD_SR/B_SS_SR - 5mV/us.
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#define MAX77812_REG_GLB_CFG2		0x34 // HOS: B_RD_SR/B_RU_SR - 5mV/us
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#define MAX77812_REG_GLB_CFG3		0x35
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/*! Protected area and settings only for MAX77812_ES2_VERSION */
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#define MAX77812_REG_GLB_CFG4		0x36 // QS: 0xBB.
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#define MAX77812_REG_GLB_CFG5		0x37 // QS: 0x39. ES2: Set to 0x3E.
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#define MAX77812_REG_GLB_CFG6		0x38 // QS: 0x88. ES2: Set to 0x90.
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#define MAX77812_REG_GLB_CFG7		0x39 // QS: 0x04.
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#define MAX77812_REG_GLB_CFG8		0x3A // QS: 0x3A. ES2: Set to 0x3A.
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#define MAX77812_REG_PROT_ACCESS	0xFD // 0x00: Lock, 0x5A: Unlock.
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#define MAX77812_REG_UNKNOWN		0xFE
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#define MAX77812_REG_EN_CTRL_MASK(n)		BIT(n)
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#define MAX77812_START_SLEW_RATE_MASK		0x07
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#define MAX77812_SHDN_SLEW_RATE_MASK		0x70
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#define MAX77812_RAMPUP_SLEW_RATE_MASK		0x07
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#define MAX77812_RAMPDOWN_SLEW_RATE_MASK	0x70
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#define MAX77812_SLEW_RATE_SHIFT			4
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#define MAX77812_OP_ACTIVE_DISCHARGE_MASK	BIT(7)
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#define MAX77812_PEAK_CURRENT_LMT_MASK		0x70
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#define MAX77812_SWITCH_FREQ_MASK			0x0C
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#define MAX77812_FORCED_PWM_MASK			BIT(1)
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#define MAX77812_SLEW_RATE_CNTRL_MASK		BIT(0)
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#define MAX77812_START_SHD_DELAY_MASK		0x1F
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#define MAX77812_VERSION_MASK				0x07
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#define MAX77812_ES2_VERSION				0x04
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#define MAX77812_QS_VERSION					0x05
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#define MAX77812_BUCK_VOLT_MASK				0xFF
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#endif
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