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/*
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 * Activity Monitor driver for Tegra X1
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 *
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 * Copyright (c) 2021 CTCaer
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include "actmon.h"
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#include "clock.h"
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#include "t210.h"
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/* Global registers */
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#define ACTMON_GLB_STATUS          0x0
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#define  ACTMON_MCCPU_MON_ACT      BIT(8)
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#define  ACTMON_MCALL_MON_ACT      BIT(9)
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#define  ACTMON_CPU_FREQ_MON_ACT   BIT(10)
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#define  ACTMON_APB_MON_ACT        BIT(12)
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#define  ACTMON_AHB_MON_ACT        BIT(13)
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#define  ACTMON_BPMP_MON_ACT       BIT(14)
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#define  ACTMON_CPU_MON_ACT        BIT(15)
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#define  ACTMON_MCCPU_INTR         BIT(25)
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#define  ACTMON_MCALL_INTR         BIT(26)
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#define  ACTMON_CPU_FREQ_INTR      BIT(27)
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#define  ACTMON_APB_INTR           BIT(28)
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#define  ACTMON_AHB_INTR           BIT(29)
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#define  ACTMON_BPMP_INTR          BIT(30)
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#define  ACTMON_CPU_INTR           BIT(31)
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#define ACTMON_GLB_PERIOD_CTRL     0x4
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#define  ACTMON_GLB_PERIOD_USEC    BIT(8)
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#define  ACTMON_GLB_PERIOD_SAMPLE(n) (((n) - 1) & 0xFF)
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/* Device Registers */
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#define ACTMON_DEV_BASE            ACTMON_BASE + 0x80
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#define  ACTMON_DEV_SIZE           0x40
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/* CTRL */
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#define  ACTMON_DEV_CTRL_K_VAL(k)                       (((k) & 7) << 10)
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#define  ACTMON_DEV_CTRL_ENB_PERIODIC                   BIT(18)
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#define  ACTMON_DEV_CTRL_AT_END_EN                      BIT(19)
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#define  ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN             BIT(20)
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#define  ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN             BIT(21)
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#define  ACTMON_DEV_CTRL_WHEN_OVERFLOW_EN               BIT(22)
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#define  ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM(n) (((n) & 7) << 23)
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#define  ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM(n) (((n) & 7) << 26)
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#define  ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN     BIT(29)
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#define  ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN     BIT(30)
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#define  ACTMON_DEV_CTRL_ENB                            BIT(31)
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/* INTR_STATUS */
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#define  ACTMON_DEV_ISTS_AVG_ABOVE_WMARK   BIT(24)
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#define  ACTMON_DEV_ISTS_AVG_BELOW_WMARK   BIT(25)
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#define  ACTMON_DEV_ISTS_WHEN_OVERFLOW     BIT(26)
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#define  ACTMON_DEV_ISTS_AT_END            BIT(29)
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#define  ACTMON_DEV_ISTS_CONSECUTIVE_LOWER BIT(30)
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#define  ACTMON_DEV_ISTS_CONSECUTIVE_UPPER BIT(31)
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/* Histogram Registers */
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#define ACTMON_HISTOGRAM_CONFIG    0x300
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#define  ACTMON_HIST_CFG_ACTIVE                   BIT(0)
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#define  ACTMON_HIST_CFG_LINEAR_MODE              BIT(1)
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#define  ACTMON_HIST_CFG_NO_UNDERFLOW_BUCKET      BIT(2)
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#define  ACTMON_HIST_CFG_STALL_ON_SINGLE_SATURATE BIT(3)
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#define  ACTMON_HIST_CFG_SHIFT(s)                 (((s) & 0x1F) << 4)
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#define  ACTMON_HIST_CFG_SOURCE(s)                (((s) & 0xF) << 12)
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#define ACTMON_HISTOGRAM_CTRL      0x304
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#define  ACTMON_HIST_CTRL_CLEAR_ALL               BIT(0)
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#define ACTMON_HISTOGRAM_DATA_BASE 0x380
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#define  ACTMON_HISTOGRAM_DATA_NUM 32
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#define ACTMON_FREQ      19200000
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#define ACTMON_PERIOD_MS 20
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#define DEV_COUNT_WEIGHT 5
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typedef struct _actmon_dev_reg_t
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{
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	vu32 ctrl;
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	vu32 upper_wnark;
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	vu32 lower_wmark;
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	vu32 init_avg;
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	vu32 avg_upper_wmark;
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	vu32 avg_lower_wmark;
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	vu32 count_weight;
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	vu32 count;
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	vu32 avg_count;
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	vu32 intr_status;
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	vu32 ctrl2;
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	vu32 rsvd[5];
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} actmon_dev_reg_t;
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void actmon_hist_enable(actmon_hist_src_t src)
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{
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	ACTMON(ACTMON_HISTOGRAM_CONFIG) = ACTMON_HIST_CFG_SOURCE(src) | ACTMON_HIST_CFG_ACTIVE;
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	ACTMON(ACTMON_HISTOGRAM_CTRL) = ACTMON_HIST_CTRL_CLEAR_ALL;
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}
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void actmon_hist_disable()
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{
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	ACTMON(ACTMON_HISTOGRAM_CONFIG) = 0;
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}
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void actmon_hist_get(u32 *histogram)
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{
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	if (histogram)
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	{
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		for (u32 i = 0; i < ACTMON_HISTOGRAM_DATA_NUM; i++)
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			histogram[i] = ACTMON(ACTMON_HISTOGRAM_DATA_BASE + i * sizeof(u32));
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	}
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}
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void actmon_dev_enable(actmon_dev_t dev)
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{
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	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
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	regs->init_avg = ACTMON_FREQ * ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT / 100;
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	regs->count_weight = DEV_COUNT_WEIGHT;
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	regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(7); // 128 samples average.
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}
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void actmon_dev_disable(actmon_dev_t dev)
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{
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	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
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	regs->ctrl = 0;
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}
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u32 actmon_dev_get_load(actmon_dev_t dev)
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{
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	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
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	// Get load-based sampling. 1 decimal point precision.
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	u32 load = regs->count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT));
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	return load;
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}
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u32 actmon_dev_get_load_avg(actmon_dev_t dev)
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{
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	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
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	// Get load-based sampling. 1 decimal point precision.
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	u32 avg_load = regs->avg_count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT));
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	return avg_load;
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}
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void atmon_dev_all_disable()
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{
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	// TODO: do a global reset?
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}
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void actmon_init()
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{
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	clock_enable_actmon();
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	// Set period.
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	ACTMON(ACTMON_GLB_PERIOD_CTRL) = ACTMON_GLB_PERIOD_SAMPLE(ACTMON_PERIOD_MS);
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}
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void actmon_end()
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{
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	clock_disable_actmon();
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}
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