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/*
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 * Copyright (c) 2018 naehrwert
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 * Copyright (c) 2018-2024 CTCaer
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef _CLOCK_H_
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#define _CLOCK_H_
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#include <utils/types.h>
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/*! Clock registers. */
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#define CLK_RST_CONTROLLER_RST_SOURCE 0x0
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#define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
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#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
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#define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U 0x18
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#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY 0x20
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#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER 0x24
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28
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#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2C
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#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
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#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
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#define CLK_RST_CONTROLLER_OSC_FREQ_DET 0x58
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#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS 0x5C
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#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL 0x60
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#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS 0x64
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#define CLK_RST_CONTROLLER_PLLC_BASE 0x80
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#define CLK_RST_CONTROLLER_PLLC_OUT 0x84
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#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
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#define CLK_RST_CONTROLLER_PLLC_MISC_1 0x8C
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#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
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#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
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#define CLK_RST_CONTROLLER_PLLP_OUTB 0xA8
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#define CLK_RST_CONTROLLER_PLLA_BASE 0xB0
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#define CLK_RST_CONTROLLER_PLLA_OUT 0xB4
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#define CLK_RST_CONTROLLER_PLLA_MISC1 0xB8
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#define CLK_RST_CONTROLLER_PLLA_MISC 0xBC
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#define CLK_RST_CONTROLLER_PLLU_BASE 0xC0
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#define CLK_RST_CONTROLLER_PLLU_OUTA 0xC4
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#define CLK_RST_CONTROLLER_PLLU_MISC 0xCC
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#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
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#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
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#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
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#define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
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#define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
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#define CLK_RST_CONTROLLER_PLLE_BASE 0xE8
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#define CLK_RST_CONTROLLER_PLLE_MISC 0xEC
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 0x100
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#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138
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#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 0x164
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 0x1D8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
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#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
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#define CLK_RST_CONTROLLER_RST_DEV_X_SET 0x290
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#define CLK_RST_CONTROLLER_RST_DEV_X_CLR 0x294
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y 0x298
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET 0x29C
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR 0x2A0
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#define CLK_RST_CONTROLLER_RST_DEVICES_Y 0x2A4
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#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2A8
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#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2AC
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#define CLK_RST_CONTROLLER_RST_DEV_L_SET 0x300
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR 0x304
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#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
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#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
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#define CLK_RST_CONTROLLER_RST_DEV_U_SET 0x310
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#define CLK_RST_CONTROLLER_RST_DEV_U_CLR 0x314
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#define CLK_RST_CONTROLLER_CLK_ENB_L_SET 0x320
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#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR 0x324
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#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
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#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR 0x32C
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#define CLK_RST_CONTROLLER_CLK_ENB_U_SET 0x330
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#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR 0x334
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#define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358
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#define CLK_RST_CONTROLLER_RST_DEVICES_W 0x35C
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V 0x360
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W 0x364
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#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 0x388
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB 0x3D0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON 0x3E8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 0x3EC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 0x3F0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
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#define CLK_RST_CONTROLLER_RST_DEV_V_SET 0x430
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
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#define CLK_RST_CONTROLLER_RST_DEV_W_SET 0x438
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#define CLK_RST_CONTROLLER_RST_DEV_W_CLR 0x43C
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0 0x480
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1 0x484
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
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#define CLK_RST_CONTROLLER_PLLE_AUX 0x48C
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#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3 0x4C0
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#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
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#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0 0x52C
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
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#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
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#define CLK_RST_CONTROLLER_PLLC4_BASE 0x5A4
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#define CLK_RST_CONTROLLER_PLLC4_MISC 0x5A8
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#define CLK_RST_CONTROLLER_PLLC_MISC_2 0x5D0
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#define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4
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#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
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#define CLK_RST_CONTROLLER_PLLMB_MISC1 0x5EC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS 0x608
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#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV 0x60C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS 0x610
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC 0x678
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC 0x698
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG 0x69C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_APE 0x6C0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK 0x6CC
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#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
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#define CLK_NO_SOURCE 0x0
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#define CLK_NOT_USED  0x0
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/*! PLL control and status bits */
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#define PLLX_BASE_LOCK       BIT(27)
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#define PLLX_BASE_REF_DIS    BIT(29)
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#define PLLX_BASE_ENABLE     BIT(30)
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#define PLLX_BASE_BYPASS     BIT(31)
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#define PLLX_MISC_LOCK_EN    BIT(18)
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#define PLLX_MISC3_IDDQ      BIT(3)
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#define PLLCX_BASE_LOCK      BIT(27)
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#define PLLCX_BASE_REF_DIS   BIT(29)
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#define PLLCX_BASE_ENABLE    BIT(30)
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#define PLLCX_BASE_BYPASS    BIT(31)
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#define PLLA_OUT0_RSTN_CLR   BIT(0)
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#define PLLA_OUT0_CLKEN      BIT(1)
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#define PLLA_BASE_IDDQ       BIT(25)
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#define PLLC_OUT1_RSTN_CLR   BIT(0)
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#define PLLC_OUT1_CLKEN      BIT(1)
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#define PLLC_MISC1_IDDQ      BIT(27)
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#define PLLC_MISC_RESET      BIT(30)
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#define PLLC4_OUT3_RSTN_CLR  BIT(0)
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#define PLLC4_OUT3_CLKEN     BIT(1)
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#define PLLC4_BASE_IDDQ      BIT(18)
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#define PLLC4_MISC_EN_LCKDET BIT(30)
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#define UTMIPLL_LOCK         BIT(31)
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/*! Clock source */
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#define CLK_SRC_DIV(d) ((d) ? ((u32)(((d) - 1) * 2)) : 0)
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/*! PTO_CLK_CNT */
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#define PTO_REF_CLK_WIN_CFG_MASK 0xF
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#define PTO_REF_CLK_WIN_CFG_16P  0xF
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#define PTO_CNT_EN               BIT(9)
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#define PTO_CNT_RST              BIT(10)
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#define PTO_CLK_ENABLE           BIT(13)
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#define PTO_SRC_SEL_SHIFT        14
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#define PTO_SRC_SEL_MASK         0x1FF
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#define PTO_DIV_SEL_MASK         (3 << 23)
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#define PTO_DIV_SEL_GATED        (0 << 23)
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#define PTO_DIV_SEL_DIV1         (1 << 23)
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#define PTO_DIV_SEL_DIV2_RISING  (2 << 23)
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#define PTO_DIV_SEL_DIV2_FALLING (3 << 23)
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#define PTO_DIV_SEL_CPU_EARLY    (0 << 23)
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#define PTO_DIV_SEL_CPU_LATE     (1 << 23)
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#define PTO_CLK_CNT_BUSY         BIT(31)
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#define PTO_CLK_CNT              0xFFFFFF
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/*! OSC_FREQ_DET */
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#define OSC_REF_CLK_WIN_CFG_MASK 0xF
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#define OSC_FREQ_DET_TRIG        BIT(31)
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#define OSC_FREQ_DET_BUSY        BIT(31)
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#define OSC_FREQ_DET_CNT         0xFFFF
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/*! PTO IDs. */
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typedef enum _clock_pto_id_t
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{
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	CLK_PTO_PCLK_SYS          = 0x06,
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	CLK_PTO_HCLK_SYS          = 0x07,
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	CLK_PTO_DMIC1             = 0x08,
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	CLK_PTO_DMIC2             = 0x09,
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	CLK_PTO_HDMI_SLOWCLK_DIV2 = 0x0A,
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	CLK_PTO_JTAG_REG          = 0x0B,
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	CLK_PTO_UTMIP_240_A       = 0x0C,
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	CLK_PTO_UTMIP_240_B       = 0x0D,
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	CLK_PTO_CCLK_G            = 0x12,
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	CLK_PTO_CCLK_G_DIV2       = 0x13,
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	CLK_PTO_MIPIBIF           = 0x14,
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	CLK_PTO_SPI1              = 0x17,
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	CLK_PTO_SPI2              = 0x18,
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	CLK_PTO_SPI3              = 0x19,
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	CLK_PTO_SPI4              = 0x1A,
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	CLK_PTO_MAUD              = 0x1B,
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	CLK_PTO_SCLK              = 0x1C,
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	CLK_PTO_SDMMC1            = 0x20,
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	CLK_PTO_SDMMC2            = 0x21,
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	CLK_PTO_SDMMC3            = 0x22,
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	CLK_PTO_SDMMC4            = 0x23,
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	CLK_PTO_EMC               = 0x24,
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	CLK_PTO_DMIC3             = 0x2A,
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	CLK_PTO_CCLK_LP           = 0x2B,
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	CLK_PTO_CCLK_LP_DIV2      = 0x2C,
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	CLK_PTO_MSELECT           = 0x2F,
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	CLK_PTO_VI_SENSOR2        = 0x33,
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	CLK_PTO_VI_SENSOR         = 0x34,
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	CLK_PTO_VIC               = 0x35,
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	CLK_PTO_VIC_SKIP          = 0x36,
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	CLK_PTO_ISP_SKIP          = 0x37,
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	CLK_PTO_ISPB_SE2_SKIP     = 0x38,
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	CLK_PTO_NVDEC_SKIP        = 0x39,
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	CLK_PTO_NVENC_SKIP        = 0x3A,
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	CLK_PTO_NVJPG_SKIP        = 0x3B,
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	CLK_PTO_TSEC_SKIP         = 0x3C,
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	CLK_PTO_TSECB_SKIP        = 0x3D,
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	CLK_PTO_SE_SKIP           = 0x3E,
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	CLK_PTO_VI_SKIP           = 0x3F,
280

281
	CLK_PTO_PLLX_OBS          = 0x40,
282
	CLK_PTO_PLLC_OBS          = 0x41,
283
	CLK_PTO_PLLM_OBS          = 0x42,
284
	CLK_PTO_PLLP_OBS          = 0x43,
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	CLK_PTO_PLLA_OBS          = 0x44,
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	CLK_PTO_PLLMB_OBS         = 0x45,
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	CLK_PTO_SATA_OOB          = 0x46,
288

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	CLK_PTO_FCPU_DVFS_DIV12_CPU = 0x48,
290

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	CLK_PTO_EQOS_AXI          = 0x4C,
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	CLK_PTO_EQOS_PTP_REF      = 0x4D,
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	CLK_PTO_EQOS_TX           = 0x4E,
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	CLK_PTO_EQOS_RX           = 0x4F,
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	CLK_PTO_CILAB             = 0x52,
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	CLK_PTO_CILCD             = 0x53,
298

299
	CLK_PTO_CILEF             = 0x55,
300
	CLK_PTO_PLLA1_PTO_OBS     = 0x56,
301
	CLK_PTO_PLLC4_PTO_OBS     = 0x57,
302

303
	CLK_PTO_PLLC2_PTO_OBS     = 0x59,
304
	CLK_PTO_PLLC3_PTO_OBS     = 0x5B,
305

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	CLK_PTO_DSIA_LP           = 0x62,
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	CLK_PTO_DSIB_LP           = 0x63,
308
	CLK_PTO_ISP               = 0x64,
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	CLK_PTO_PEX_PAD           = 0x65,
310

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	CLK_PTO_MC                = 0x6A,
312

313
	CLK_PTO_ACTMON            = 0x6B,
314
	CLK_PTO_CSITE             = 0x6C,
315
	CLK_PTO_VI_I2C            = 0x6D,
316

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	CLK_PTO_HOST1X            = 0x6F,
318

319
	CLK_PTO_QSPI_2X           = 0x71,
320
	CLK_PTO_NVDEC             = 0x72,
321
	CLK_PTO_NVJPG             = 0x73,
322
	CLK_PTO_SE                = 0x74,
323
	CLK_PTO_SOC_THERM         = 0x75,
324

325
	CLK_PTO_TSEC              = 0x77,
326
	CLK_PTO_TSECB             = 0x78,
327
	CLK_PTO_VI                = 0x79,
328
	CLK_PTO_LA                = 0x7A,
329
	CLK_PTO_SCLK_SKIP         = 0x7B,
330

331
	CLK_PTO_ADSP_SKIP         = 0x7C,
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	CLK_PTO_QSPI              = 0x7D,
333

334
	CLK_PTO_SDMMC2_SHAPER     = 0x7E,
335
	CLK_PTO_SDMMC4_SHAPER     = 0x7F,
336
	CLK_PTO_I2S1              = 0x80,
337
	CLK_PTO_I2S2              = 0x81,
338
	CLK_PTO_I2S3              = 0x82,
339
	CLK_PTO_I2S4              = 0x83,
340
	CLK_PTO_I2S5              = 0x84,
341
	CLK_PTO_AHUB              = 0x85,
342
	CLK_PTO_APE               = 0x86,
343

344
	CLK_PTO_DVFS_SOC          = 0x88,
345
	CLK_PTO_DVFS_REF          = 0x89,
346
	CLK_PTO_ADSP_CLK          = 0x8A,
347
	CLK_PTO_ADSP_DIV2_CLK     = 0x8B,
348

349
	CLK_PTO_SPDIF_OUT         = 0x8F,
350
	CLK_PTO_SPDIF_IN          = 0x90,
351
	CLK_PTO_UART_FST_MIPI_CAL = 0x91,
352
	CLK_PTO_SYS2HSIO_SATA_CLK = 0x92,
353
	CLK_PTO_PWM               = 0x93,
354
	CLK_PTO_I2C1              = 0x94,
355
	CLK_PTO_I2C2              = 0x95,
356
	CLK_PTO_I2C3              = 0x96,
357
	CLK_PTO_I2C4              = 0x97,
358
	CLK_PTO_I2C5              = 0x98,
359
	CLK_PTO_I2C6              = 0x99,
360
	CLK_PTO_I2C_SLOW          = 0x9A,
361
	CLK_PTO_UARTAPE           = 0x9B,
362

363
	CLK_PTO_EXTPERIPH1        = 0x9D,
364
	CLK_PTO_EXTPERIPH2        = 0x9E,
365
	CLK_PTO_EXTPERIPH3        = 0x9F,
366
	CLK_PTO_ENTROPY           = 0xA0,
367
	CLK_PTO_UARTA             = 0xA1,
368
	CLK_PTO_UARTB             = 0xA2,
369
	CLK_PTO_UARTC             = 0xA3,
370
	CLK_PTO_UARTD             = 0xA4,
371
	CLK_PTO_OWR               = 0xA5,
372
	CLK_PTO_TSENSOR           = 0xA6,
373
	CLK_PTO_HDA2CODEC_2X      = 0xA7,
374
	CLK_PTO_HDA               = 0xA8,
375
	CLK_PTO_EMC_LATENCY       = 0xA9,
376
	CLK_PTO_EMC_DLL           = 0xAA,
377
	CLK_PTO_SDMMC_LEGACY_TM   = 0xAB,
378
	CLK_PTO_DBGAPB            = 0xAC,
379

380
	CLK_PTO_SOR0              = 0xC0,
381
	CLK_PTO_SOR1              = 0xC1,
382
	CLK_PTO_HDMI              = 0xC2,
383

384
	CLK_PTO_DISP2             = 0xC4,
385
	CLK_PTO_DISP1             = 0xC5,
386

387
	CLK_PTO_PLLD_OBS          = 0xCA,
388
	CLK_PTO_PLLD2_PTO_OBS     = 0xCC,
389
	CLK_PTO_PLLDP_OBS         = 0xCE,
390
	CLK_PTO_PLLE_OBS          = 0x10A,
391
	CLK_PTO_PLLU_OBS          = 0x10C,
392
	CLK_PTO_PLLREFE_OBS       = 0x10E,
393

394
	CLK_PTO_XUSB_FALCON       = 0x110,
395
	CLK_PTO_XUSB_CLK480M_HSIC = 0x111,
396
	CLK_PTO_USB_L0_RX         = 0x112,
397
	CLK_PTO_USB_L3_RX         = 0x113,
398
	CLK_PTO_USB_RX            = 0x114,
399
	CLK_PTO_USB3_L0_TXCLKREF  = 0x115,
400
	CLK_PTO_PEX_TXCLKREF_SWITCH_TMS = 0x116,
401
	CLK_PTO_PEX_TXCLKREF_SWITCH_GRP0 = 0x117,
402
	CLK_PTO_PEX_TXCLKREF_SWITCH_GRP1 = 0x118,
403
	CLK_PTO_PEX_TXCLKREF_SWITCH_GRP2 = 0x119,
404
	CLK_PTO_PEX_L4_RX         = 0x11A,
405
	CLK_PTO_PEX_TXCLKREF      = 0x11B,
406
	CLK_PTO_PEX_TXCLKREF_DIV2 = 0x11C,
407
	CLK_PTO_PEX_TXCLKREF2     = 0x11D,
408
	CLK_PTO_PEX_L0_RX         = 0x11E,
409
	CLK_PTO_PEX_L1_RX         = 0x11F,
410
	CLK_PTO_PEX_L2_RX         = 0x120,
411
	CLK_PTO_PEX_L3_RX         = 0x121,
412
	CLK_PTO_SATA_TXCLKREF     = 0x122,
413
	CLK_PTO_SATA_TXCLKREF_DIV2 = 0x123,
414
	CLK_PTO_USB_L5_RX         = 0x124,
415
	CLK_PTO_SATA_TX           = 0x125,
416
	CLK_PTO_SATA_L0_RX        = 0x126,
417

418
	CLK_PTO_USB3_L1_TXCLKREF  = 0x129,
419
	CLK_PTO_USB3_L7_TXCLKREF  = 0x12A,
420
	CLK_PTO_USB3_L7_RX        = 0x12B,
421
	CLK_PTO_USB3_TX           = 0x12C,
422
	CLK_PTO_UTMIP_PLL_PAD     = 0x12D,
423

424
	CLK_PTO_XUSB_FS           = 0x136,
425
	CLK_PTO_XUSB_SS_HOST_DEV  = 0x137,
426
	CLK_PTO_XUSB_CORE_HOST    = 0x138,
427
	CLK_PTO_XUSB_CORE_DEV     = 0x139,
428

429
	CLK_PTO_USB3_L2_TXCLKREF  = 0x13C,
430
	CLK_PTO_USB3_L3_TXCLKREF  = 0x13D,
431
	CLK_PTO_USB_L4_RX         = 0x13E,
432
	CLK_PTO_USB_L6_RX         = 0x13F,
433

434
	/*
435
	 * PLL need PTO enabled in MISC registers.
436
	 * Normal div is 2 so result is multiplied with it.
437
	 */
438
	CLK_PTO_PLLC_DIV2    = 0x01,
439
	CLK_PTO_PLLM_DIV2    = 0x02,
440
	CLK_PTO_PLLP_DIV2    = 0x03,
441
	CLK_PTO_PLLA_DIV2    = 0x04,
442
	CLK_PTO_PLLX_DIV2    = 0x05,
443

444
	CLK_PTO_PLLMB_DIV2   = 0x25,
445

446
	CLK_PTO_PLLC4_DIV2   = 0x51,
447

448
	CLK_PTO_PLLA1_DIV2   = 0x55,
449
	CLK_PTO_PLLC2_DIV2   = 0x58,
450
	CLK_PTO_PLLC3_DIV2   = 0x5A,
451

452
	CLK_PTO_PLLD_DIV2    = 0xCB,
453
	CLK_PTO_PLLD2_DIV2   = 0xCD,
454
	CLK_PTO_PLLDP_DIV2   = 0xCF,
455

456
	CLK_PTO_PLLE_DIV2    = 0x10B,
457

458
	CLK_PTO_PLLU_DIV2    = 0x10D,
459

460
	CLK_PTO_PLLREFE_DIV2 = 0x10F,
461
} clock_pto_id_t;
462

463
/*
464
 * CLOCK Peripherals:
465
 * L   0 -  31
466
 * H  32 -  63
467
 * U  64 -  95
468
 * V  96 - 127
469
 * W 128 - 159
470
 * X 160 - 191
471
 * Y 192 - 223
472
 */
473

474
enum CLK_L_DEV
475
{
476
	CLK_L_CPU     = 0, // Only reset. Deprecated.
477
	CLK_L_BPMP    = 1, // Only reset.
478
	CLK_L_SYS     = 2, // Only reset.
479
	CLK_L_ISPB    = 3,
480
	CLK_L_RTC     = 4,
481
	CLK_L_TMR     = 5,
482
	CLK_L_UARTA   = 6,
483
	CLK_L_UARTB   = 7,
484
	CLK_L_GPIO    = 8,
485
	CLK_L_SDMMC2  = 9,
486
	CLK_L_SPDIF   = 10,
487
	CLK_L_I2S2    = 11, // I2S1
488
	CLK_L_I2C1    = 12,
489
	CLK_L_NDFLASH = 13, // HIDDEN.
490
	CLK_L_SDMMC1  = 14,
491
	CLK_L_SDMMC4  = 15,
492
	CLK_L_TWC     = 16, // HIDDEN.
493
	CLK_L_PWM     = 17,
494
	CLK_L_I2S3    = 18,
495
	CLK_L_EPP     = 19, // HIDDEN.
496
	CLK_L_VI      = 20,
497
	CLK_L_2D      = 21, // HIDDEN.
498
	CLK_L_USBD    = 22,
499
	CLK_L_ISP     = 23,
500
	CLK_L_3D      = 24, // HIDDEN.
501
	CLK_L_IDE     = 25, // RESERVED.
502
	CLK_L_DISP2   = 26,
503
	CLK_L_DISP1   = 27,
504
	CLK_L_HOST1X  = 28,
505
	CLK_L_VCP     = 29, // HIDDEN.
506
	CLK_L_I2S1    = 30, // I2S0
507
	CLK_L_BPMP_CACHE_CTRL = 31, // CONTROLLER
508
};
509

510
enum CLK_H_DEV
511
{
512
	CLK_H_MEM      = 0, // MC.
513
	CLK_H_AHBDMA   = 1,
514
	CLK_H_APBDMA   = 2,
515
	//CLK_H_       = 3,
516
	CLK_H_KBC      = 4, // HIDDEN.
517
	CLK_H_STAT_MON = 5,
518
	CLK_H_PMC      = 6,
519
	CLK_H_FUSE     = 7,
520
	CLK_H_KFUSE    = 8,
521
	CLK_H_SPI1     = 9,
522
	CLK_H_SNOR     = 10, // HIDDEN.
523
	CLK_H_JTAG2TBC = 11,
524
	CLK_H_SPI2     = 12,
525
	CLK_H_XIO      = 13, // HIDDEN.
526
	CLK_H_SPI3     = 14,
527
	CLK_H_I2C5     = 15,
528
	CLK_H_DSI      = 16,
529
	CLK_H_TVO      = 17, // RESERVED.
530
	CLK_H_HSI      = 18, // HIDDEN.
531
	CLK_H_HDMI     = 19, // HIDDEN.
532
	CLK_H_CSI      = 20,
533
	CLK_H_TVDAC    = 21, // RESERVED.
534
	CLK_H_I2C2     = 22,
535
	CLK_H_UARTC    = 23,
536
	CLK_H_MIPI_CAL = 24,
537
	CLK_H_EMC      = 25,
538
	CLK_H_USB2     = 26,
539
	CLK_H_USB3     = 27, // HIDDEN.
540
	CLK_H_MPE      = 28, // HIDDEN.
541
	CLK_H_VDE      = 29, // HIDDEN.
542
	CLK_H_BSEA     = 30, // HIDDEN.
543
	CLK_H_BSEV     = 31,
544
};
545

546
enum CLK_U_DEV
547
{
548
	CLK_U_SPEEDO         = 0, // RESERVED.
549
	CLK_U_UARTD          = 1,
550
	CLK_U_UARTE          = 2, // HIDDEN.
551
	CLK_U_I2C3           = 3,
552
	CLK_U_SPI4           = 4,
553
	CLK_U_SDMMC3         = 5,
554
	CLK_U_PCIE           = 6,
555
	CLK_U_OWR            = 7, // RESERVED.
556
	CLK_U_AFI            = 8,
557
	CLK_U_CSITE          = 9,
558
	CLK_U_PCIEXCLK       = 10, // Only reset.
559
	CLK_U_BPMPUCQ        = 11, // HIDDEN.
560
	CLK_U_LA             = 12,
561
	CLK_U_TRACECLKIN     = 13, // HIDDEN.
562
	CLK_U_SOC_THERM      = 14,
563
	CLK_U_DTV            = 15,
564
	CLK_U_NAND_SPEED     = 16, // HIDDEN.
565
	CLK_U_I2C_SLOW       = 17,
566
	CLK_U_DSIB           = 18,
567
	CLK_U_TSEC           = 19,
568
	CLK_U_IRAMA          = 20,
569
	CLK_U_IRAMB          = 21,
570
	CLK_U_IRAMC          = 22,
571
	CLK_U_IRAMD          = 23, // EMUCIF ON RESET
572
	CLK_U_BPMP_CACHE_RAM = 24,
573
	CLK_U_XUSB_HOST      = 25,
574
	CLK_U_CLK_M_DOUBLER  = 26,
575
	CLK_U_MSENC          = 27, // HIDDEN.
576
	CLK_U_SUS_OUT        = 28,
577
	CLK_U_DEV2_OUT       = 29,
578
	CLK_U_DEV1_OUT       = 30,
579
	CLK_U_XUSB_DEV       = 31,
580
};
581

582
enum CLK_V_DEV
583
{
584
	CLK_V_CPUG          = 0,
585
	CLK_V_CPULP         = 1, // Reserved.
586
	CLK_V_3D2           = 2, // HIDDEN.
587
	CLK_V_MSELECT       = 3,
588
	CLK_V_TSENSOR       = 4,
589
	CLK_V_I2S4          = 5,
590
	CLK_V_I2S5          = 6,
591
	CLK_V_I2C4          = 7,
592
	CLK_V_SPI5          = 8, // HIDDEN.
593
	CLK_V_SPI6          = 9, // HIDDEN.
594
	CLK_V_AHUB          = 10, // AUDIO.
595
	CLK_V_APB2APE       = 11, // APBIF.
596
	CLK_V_DAM0          = 12, // HIDDEN.
597
	CLK_V_DAM1          = 13, // HIDDEN.
598
	CLK_V_DAM2          = 14, // HIDDEN.
599
	CLK_V_HDA2CODEC_2X  = 15,
600
	CLK_V_ATOMICS       = 16,
601
	//CLK_V_            = 17,
602
	//CLK_V_            = 18,
603
	//CLK_V_            = 19,
604
	//CLK_V_            = 20,
605
	//CLK_V_            = 21,
606
	CLK_V_SPDIF_DOUBLER = 22,
607
	CLK_V_ACTMON        = 23,
608
	CLK_V_EXTPERIPH1    = 24,
609
	CLK_V_EXTPERIPH2    = 25,
610
	CLK_V_EXTPERIPH3    = 26,
611
	CLK_V_SATA_OOB      = 27,
612
	CLK_V_SATA          = 28,
613
	CLK_V_HDA           = 29,
614
	CLK_V_TZRAM         = 30, // HIDDEN.
615
	CLK_V_SE            = 31, // HIDDEN.
616
};
617

618
enum CLK_W_DEV
619
{
620
	CLK_W_HDA2HDMICODEC = 0,
621
	CLK_W_RESERVED0     = 1, //satacoldrstn
622
	CLK_W_PCIERX0       = 2,
623
	CLK_W_PCIERX1       = 3,
624
	CLK_W_PCIERX2       = 4,
625
	CLK_W_PCIERX3       = 5,
626
	CLK_W_PCIERX4       = 6,
627
	CLK_W_PCIERX5       = 7,
628
	CLK_W_CEC           = 8,
629
	CLK_W_PCIE2_IOBIST  = 9,
630
	CLK_W_EMC_IOBIST    = 10,
631
	CLK_W_HDMI_IOBIST   = 11, // HIDDEN.
632
	CLK_W_SATA_IOBIST   = 12,
633
	CLK_W_MIPI_IOBIST   = 13,
634
	CLK_W_XUSB_PADCTL   = 14, // Only reset.
635
	CLK_W_XUSB          = 15,
636
	CLK_W_CILAB         = 16,
637
	CLK_W_CILCD         = 17,
638
	CLK_W_CILEF         = 18,
639
	CLK_W_DSIA_LP       = 19,
640
	CLK_W_DSIB_LP       = 20,
641
	CLK_W_ENTROPY       = 21,
642
	CLK_W_DDS           = 22, // HIDDEN.
643
	//CLK_W_            = 23,
644
	CLK_W_DP2           = 24, // HIDDEN.
645
	CLK_W_AMX0          = 25, // HIDDEN.
646
	CLK_W_ADX0          = 26, // HIDDEN.
647
	CLK_W_DVFS          = 27,
648
	CLK_W_XUSB_SS       = 28,
649
	CLK_W_EMC_LATENCY   = 29,
650
	CLK_W_MC1           = 30,
651
	//CLK_W_            = 31,
652
};
653

654
enum CLK_X_DEV
655
{
656
	CLK_X_SPARE             = 0,
657
	CLK_X_DMIC1             = 1,
658
	CLK_X_DMIC2             = 2,
659
	CLK_X_ETR               = 3,
660
	CLK_X_CAM_MCLK          = 4,
661
	CLK_X_CAM_MCLK2         = 5,
662
	CLK_X_I2C6              = 6,
663
	CLK_X_MC_CAPA           = 7, // MC DAISY CHAIN1
664
	CLK_X_MC_CBPA           = 8, // MC DAISY CHAIN2
665
	CLK_X_MC_CPU            = 9,
666
	CLK_X_MC_BBC            = 10,
667
	CLK_X_VIM2_CLK          = 11,
668
	//CLK_X_                = 12,
669
	CLK_X_MIPIBIF           = 13, //RESERVED
670
	CLK_X_EMC_DLL           = 14,
671
	//CLK_X_                = 15,
672
	CLK_X_HDMI_AUDIO        = 16, // HIDDEN.
673
	CLK_X_UART_FST_MIPI_CAL = 17,
674
	CLK_X_VIC               = 18,
675
	//CLK_X_                = 19,
676
	CLK_X_ADX1              = 20, // HIDDEN.
677
	CLK_X_DPAUX             = 21,
678
	CLK_X_SOR0              = 22,
679
	CLK_X_SOR1              = 23,
680
	CLK_X_GPU               = 24,
681
	CLK_X_DBGAPB            = 25,
682
	CLK_X_HPLL_ADSP         = 26,
683
	CLK_X_PLLP_ADSP         = 27,
684
	CLK_X_PLLA_ADSP         = 28,
685
	CLK_X_PLLG_REF          = 29,
686
	//CLK_X_ = 30,
687
	//CLK_X_ = 31,
688
};
689

690
enum CLK_Y_DEV
691
{
692
	CLK_Y_SPARE1          = 0,
693
	CLK_Y_SDMMC_LEGACY_TM = 1,
694
	CLK_Y_NVDEC           = 2,
695
	CLK_Y_NVJPG           = 3,
696
	CLK_Y_AXIAP           = 4,
697
	CLK_Y_DMIC3           = 5,
698
	CLK_Y_APE             = 6,
699
	CLK_Y_ADSP            = 7,
700
	CLK_Y_MC_CDPA         = 8, // MC DAISY CHAIN4
701
	CLK_Y_MC_CCPA         = 9, // MC DAISY CHAIN3
702
	CLK_Y_MAUD            = 10,
703
	//CLK_Y_              = 11,
704
	CLK_Y_SATA_USB_UPHY   = 12, // Only reset.
705
	CLK_Y_PEX_USB_UPHY    = 13, // Only reset.
706
	CLK_Y_TSECB           = 14,
707
	CLK_Y_DPAUX1          = 15,
708
	CLK_Y_VI_I2C          = 16,
709
	CLK_Y_HSIC_TRK        = 17,
710
	CLK_Y_USB2_TRK        = 18,
711
	CLK_Y_QSPI            = 19,
712
	CLK_Y_UARTAPE         = 20,
713
	CLK_Y_ADSPINTF        = 21, // Only reset.
714
	CLK_Y_ADSPPERIPH      = 22, // Only reset.
715
	CLK_Y_ADSPDBG         = 23, // Only reset.
716
	CLK_Y_ADSPWDT         = 24, // Only reset.
717
	CLK_Y_ADSPSCU         = 25, // Only reset.
718
	CLK_Y_ADSPNEON        = 26,
719
	CLK_Y_NVENC           = 27,
720
	CLK_Y_IQC2            = 28,
721
	CLK_Y_IQC1            = 29,
722
	CLK_Y_SOR_SAFE        = 30,
723
	CLK_Y_PLLP_OUT_CPU    = 31,
724
};
725

726
/*! Generic clock descriptor. */
727
typedef struct _clk_rst_t
728
{
729
	u16 reset;
730
	u16 enable;
731
	u16 source;
732
	u8 index;
733
	u8 clk_src;
734
	u8 clk_div;
735
} clk_rst_t;
736

737
/*! Generic clock enable/disable. */
738
void clock_enable(const clk_rst_t *clk);
739
void clock_disable(const clk_rst_t *clk);
740

741
/*! Clock control for specific hardware portions. */
742
void clock_enable_fuse(bool enable);
743
void clock_enable_uart(u32 idx);
744
void clock_disable_uart(u32 idx);
745
int  clock_uart_use_src_div(u32 idx, u32 baud);
746
void clock_enable_i2c(u32 idx);
747
void clock_disable_i2c(u32 idx);
748
void clock_enable_se();
749
void clock_enable_tzram();
750
void clock_enable_host1x();
751
void clock_disable_host1x();
752
void clock_enable_tsec();
753
void clock_disable_tsec();
754
void clock_enable_nvdec();
755
void clock_disable_nvdec();
756
void clock_enable_nvjpg();
757
void clock_disable_nvjpg();
758
void clock_enable_vic();
759
void clock_disable_vic();
760
void clock_enable_sor_safe();
761
void clock_disable_sor_safe();
762
void clock_enable_sor0();
763
void clock_disable_sor0();
764
void clock_enable_sor1();
765
void clock_disable_sor1();
766
void clock_enable_kfuse();
767
void clock_disable_kfuse();
768
void clock_enable_cl_dvfs();
769
void clock_disable_cl_dvfs();
770
void clock_enable_coresight();
771
void clock_disable_coresight();
772
void clock_enable_pwm();
773
void clock_disable_pwm();
774
void clock_enable_apbdma();
775
void clock_disable_apbdma();
776
void clock_enable_ahbdma();
777
void clock_disable_ahbdma();
778
void clock_enable_actmon();
779
void clock_disable_actmon();
780
void clock_enable_extperiph1();
781
void clock_disable_extperiph1();
782
void clock_enable_extperiph2();
783
void clock_disable_extperiph2();
784

785
void clock_enable_plld(u32 divp, u32 divn, bool lowpower, bool tegra_t210);
786
void clock_enable_pllx();
787
void clock_enable_pllc(u32 divn);
788
void clock_disable_pllc();
789
void clock_enable_pllu();
790
void clock_disable_pllu();
791
void clock_enable_utmipll();
792

793
void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val);
794
void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type);
795
int  clock_sdmmc_is_not_reset_and_enabled(u32 id);
796
void clock_sdmmc_enable(u32 id, u32 val);
797
void clock_sdmmc_disable(u32 id);
798

799
u32 clock_get_osc_freq();
800
u32 clock_get_dev_freq(clock_pto_id_t id);
801

802
#endif
803

804