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/*
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 * Copyright (c) 2020 CTCaer
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include <soc/hw_init.h>
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#include <soc/pmc.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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void pmc_scratch_lock(pmc_sec_lock_t lock_mask)
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{
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	// Lock Private key disable, Fuse write enable, MC carveout, Warmboot PA id and Warmboot address.
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	// Happens on T210B01 LP0 always.
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	if (lock_mask & PMC_SEC_LOCK_MISC)
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	{
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		PMC(APBDEV_PMC_SEC_DISABLE)  |= 0x700FF0;   // RW lock: 0-3.
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		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0xFC000000; // RW lock: 21-23.
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		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0x3F0FFF00; // RW lock: 28-33, 36-38.
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		PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xC000000;  // RW lock: 85.
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		// Default: 0xFF00FF00: RW lock: 108-111, 116-119. Gets locked in LP0.
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		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF005500; // W lock: 108-111, RW lock: 116-119.
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 	}
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 	// Happens on T210B01 LP0 always.
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	if (lock_mask & PMC_SEC_LOCK_LP0_PARAMS)
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	{
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		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x3FCFFFF;  // RW lock: 8-15, 17-20. L4T expects 8-15 as write locked only.
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		PMC(APBDEV_PMC_SEC_DISABLE4) |= 0x3F3FFFFF; // RW lock: 40-50, 52-54.
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		PMC(APBDEV_PMC_SEC_DISABLE5)  = 0xFFFFFFFF; // RW lock: 56-71.
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		PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xF3FFC00F; // RW lock: 72-73, 79-84, 86-87.
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		PMC(APBDEV_PMC_SEC_DISABLE7) |= 0x3FFFFF;   // RW lock: 88-98.
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		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF;       // RW lock: 104-107.
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	}
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	if (lock_mask & PMC_SEC_LOCK_RST_VECTOR)
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		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xF00000;   // RW lock: 34-35.
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	if (lock_mask & PMC_SEC_LOCK_CARVEOUTS)
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	{
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		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x30000;    // RW lock: 16.
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		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xC0000000; // RW lock: 39.
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		PMC(APBDEV_PMC_SEC_DISABLE4) |= 0xC0C00000; // RW lock: 51, 55.
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		PMC(APBDEV_PMC_SEC_DISABLE6) |= 0x3FF0;     // RW lock: 74-78.
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		PMC(APBDEV_PMC_SEC_DISABLE7) |= 0xFFC00000; // RW lock: 99-103.
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	}
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	// HOS specific.
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	if (lock_mask & PMC_SEC_LOCK_TZ_CMAC_W)
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		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0x550000;   // W lock: 112-115.
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	if (lock_mask & PMC_SEC_LOCK_TZ_CMAC_R)
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		PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xAA0000;   // R lock: 112-115.
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	if (lock_mask & PMC_SEC_LOCK_TZ_KEK_W)
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		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0x55;       // W lock: 24-27.
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	if (lock_mask & PMC_SEC_LOCK_TZ_KEK_R)
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		PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xAA;       // R lock: 24-27.
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	// End of HOS specific.
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	if (lock_mask & PMC_SEC_LOCK_SE_SRK)
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		PMC(APBDEV_PMC_SEC_DISABLE)  |= 0xFF000;    // RW lock: 4-7
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	if (lock_mask & PMC_SEC_LOCK_SE2_SRK_B01)
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		PMC(APBDEV_PMC_SEC_DISABLE9)  |= 0x3FC;     // RW lock: 120-123 (T210B01). LP0 also sets global bits (b0-1).
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	if (lock_mask & PMC_SEC_LOCK_MISC_B01)
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		PMC(APBDEV_PMC_SEC_DISABLE10) = 0xFFFFFFFF; // RW lock: 135-150. Happens on T210B01 LP0 always.
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	if (lock_mask & PMC_SEC_LOCK_CARVEOUTS_L4T)
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		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x5555;     // W: 8-15 LP0 and Carveouts. Superseded by LP0 lock.
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	// NVTBOOT misses APBDEV_PMC_SCRATCH_WRITE_LOCK_DISABLE_STICKY. bit0: SCRATCH_WR_DIS_ON.
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	// They could also use the NS write disable registers instead.
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	if (lock_mask & PMC_SEC_LOCK_LP0_PARAMS_B01)
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	{
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE0) |= 0xCBCFE0;   // W lock: 5-11, 14-17, 19, 22-23.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1) |= 0x583FF;    // W lock: 24-33, 39-40, 42.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE2) |= 0x1BE;      // W lock: 44-48, 50-51.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE3)  = 0xFFFFFFFF; // W lock: 56-87.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE4) |= 0xFFFFFFF;  // W lock: 88-115.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE5) |= 0xFFFFFFF8; // W lock: 123-151.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE6)  = 0xFFFFFFFF; // W lock: 152-183.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE7) |= 0xFC00FFFF; // W lock: 184-199, 210-215.
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		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE8) |= 0xF;        // W lock: 216-219.
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	}
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}
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int pmc_enable_partition(pmc_power_rail_t part, u32 enable)
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{
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	u32 part_mask = BIT(part);
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	u32 desired_state = enable << part;
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	// Check if the partition has the state we want.
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	if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
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		return 1;
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	u32 i = 5001;
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	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
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	{
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		usleep(1);
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		i--;
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		if (i < 1)
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			return 0;
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	}
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	// Toggle power gating.
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	PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | 0x100;
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	i = 5001;
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	while (i > 0)
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	{
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		if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
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			break;
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		usleep(1);
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		i--;
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	}
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	return 1;
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}
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