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/*
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 * Copyright (c) 2020 CTCaer
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 */
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#ifndef __TEGRA210B01_SDRAM_PARAM_H__
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#define __TEGRA210B01_SDRAM_PARAM_H__
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#include "types.h"
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struct sdram_params_t210b01
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{
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	/* Specifies the type of memory device */
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	u32 memory_type;
23

24
	/* MC/EMC clock source configuration */
25

26
	/* Specifies the M value for PllM */
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	u32 pllm_input_divider;
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	/* Specifies the N value for PllM */
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	u32 pllm_feedback_divider;
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	/* Specifies the time to wait for PLLM to lock (in microseconds) */
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	u32 pllm_stable_time;
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	/* Specifies misc. control bits */
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	u32 pllm_setup_control;
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	/* Specifies the P value for PLLM */
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	u32 pllm_post_divider;
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	/* Specifies value for Charge Pump Gain Control */
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	u32 pllm_kcp;
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	/* Specifies VCO gain */
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	u32 pllm_kvco;
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	/* Spare BCT param */
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	u32 emc_bct_spare0;
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	/* Spare BCT param */
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	u32 emc_bct_spare1;
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	/* Spare BCT param */
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	u32 emc_bct_spare2;
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	/* Spare BCT param */
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	u32 emc_bct_spare3;
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	/* Spare BCT param */
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	u32 emc_bct_spare4;
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	/* Spare BCT param */
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	u32 emc_bct_spare5;
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	/* Spare BCT param */
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	u32 emc_bct_spare6;
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	/* Spare BCT param */
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	u32 emc_bct_spare7;
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	/* Spare BCT param */
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	u32 emc_bct_spare8;
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	/* Spare BCT param */
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	u32 emc_bct_spare9;
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	/* Spare BCT param */
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	u32 emc_bct_spare10;
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	/* Spare BCT param */
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	u32 emc_bct_spare11;
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	/* Spare BCT param */
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	u32 emc_bct_spare12;
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	/* Spare BCT param */
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	u32 emc_bct_spare13;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure0;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure1;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure2;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure3;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure4;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure5;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure6;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure7;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure8;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure9;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure10;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure11;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure12;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure13;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure14;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure15;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure16;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure17;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure18;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure19;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure20;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure21;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure22;
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	/* Spare BCT param */
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	u32 emc_bct_spare_secure23;
116

117
	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
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	u32 emc_clock_source;
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	u32 emc_clock_source_dll;
120

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	/* Defines possible override for PLLLM_MISC2 */
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	u32 clk_rst_pllm_misc20_override;
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	/* enables override for PLLLM_MISC2 */
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	u32 clk_rst_pllm_misc20_override_enable;
125
	/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
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	u32 clear_clock2_mc1;
127

128
	/* Auto-calibration of EMC pads */
129

130
	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
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	u32 emc_auto_cal_interval;
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	/*
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	 * Specifies the value for EMC_AUTO_CAL_CONFIG
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	 * Note: Trigger bits are set by the SDRAM code.
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	 */
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	u32 emc_auto_cal_config;
137

138
	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
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	u32 emc_auto_cal_config2;
140

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	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
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	u32 emc_auto_cal_config3;
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	u32 emc_auto_cal_config4;
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	u32 emc_auto_cal_config5;
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	u32 emc_auto_cal_config6;
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	u32 emc_auto_cal_config7;
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	u32 emc_auto_cal_config8;
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	u32 emc_auto_cal_config9;
149

150
	/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
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	u32 emc_auto_cal_vref_sel0;
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	u32 emc_auto_cal_vref_sel1;
153

154
	/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
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	u32 emc_auto_cal_channel;
156

157
	/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
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	u32 emc_pmacro_auto_cal_cfg0;
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	u32 emc_pmacro_auto_cal_cfg1;
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	u32 emc_pmacro_auto_cal_cfg2;
161

162
	u32 emc_pmacro_rx_term;
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	u32 emc_pmacro_dq_tx_drive;
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	u32 emc_pmacro_ca_tx_drive;
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	u32 emc_pmacro_cmd_tx_drive;
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	u32 emc_pmacro_auto_cal_common;
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	u32 emc_pmacro_zcrtl;
168

169
	/*
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	 * Specifies the time for the calibration
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	 * to stabilize (in microseconds)
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	 */
173
	u32 emc_auto_cal_wait;
174

175
	u32 emc_xm2_comp_pad_ctrl;
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	u32 emc_xm2_comp_pad_ctrl2;
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	u32 emc_xm2_comp_pad_ctrl3;
178

179
	/*
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	 * DRAM size information
181
	 * Specifies the value for EMC_ADR_CFG
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	 */
183
	u32 emc_adr_cfg;
184

185
	/*
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	 * Specifies the time to wait after asserting pin
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	 * CKE (in microseconds)
188
	 */
189
	u32 emc_pin_program_wait;
190
	/* Specifies the extra delay before/after pin RESET/CKE command */
191
	u32 emc_pin_extra_wait;
192

193
	u32 emc_pin_gpio_enable;
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	u32 emc_pin_gpio;
195

196
	/*
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	 * Specifies the extra delay after the first writing
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	 * of EMC_TIMING_CONTROL
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	 */
200
	u32 emc_timing_control_wait;
201

202
	/* Timing parameters required for the SDRAM */
203

204
	/* Specifies the value for EMC_RC */
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	u32 emc_rc;
206
	/* Specifies the value for EMC_RFC */
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	u32 emc_rfc;
208

209
	u32 emc_rfc_pb;
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	u32 emc_ref_ctrl2;
211

212
	/* Specifies the value for EMC_RFC_SLR */
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	u32 emc_rfc_slr;
214
	/* Specifies the value for EMC_RAS */
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	u32 emc_ras;
216
	/* Specifies the value for EMC_RP */
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	u32 emc_rp;
218
	/* Specifies the value for EMC_R2R */
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	u32 emc_r2r;
220
	/* Specifies the value for EMC_W2W */
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	u32 emc_w2w;
222
	/* Specifies the value for EMC_R2W */
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	u32 emc_r2w;
224
	/* Specifies the value for EMC_W2R */
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	u32 emc_w2r;
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	/* Specifies the value for EMC_R2P */
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	u32 emc_r2p;
228
	/* Specifies the value for EMC_W2P */
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	u32 emc_w2p;
230

231
	u32 emc_tppd;
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	u32 emc_trtm;
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	u32 emc_twtm;
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	u32 emc_tratm;
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	u32 emc_twatm;
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	u32 emc_tr2ref;
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	u32 emc_ccdmw;
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239
	/* Specifies the value for EMC_RD_RCD */
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	u32 emc_rd_rcd;
241
	/* Specifies the value for EMC_WR_RCD */
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	u32 emc_wr_rcd;
243
	/* Specifies the value for EMC_RRD */
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	u32 emc_rrd;
245
	/* Specifies the value for EMC_REXT */
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	u32 emc_rext;
247
	/* Specifies the value for EMC_WEXT */
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	u32 emc_wext;
249
	/* Specifies the value for EMC_WDV */
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	u32 emc_wdv;
251

252
	u32 emc_wdv_chk;
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	u32 emc_wsv;
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	u32 emc_wev;
255

256
	/* Specifies the value for EMC_WDV_MASK */
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	u32 emc_wdv_mask;
258

259
	u32 emc_ws_duration;
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	u32 emc_we_duration;
261

262
	/* Specifies the value for EMC_QUSE */
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	u32 emc_quse;
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	/* Specifies the value for EMC_QUSE_WIDTH */
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	u32 emc_quse_width;
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	/* Specifies the value for EMC_IBDLY */
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	u32 emc_ibdly;
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269
	u32 emc_obdly;
270

271
	/* Specifies the value for EMC_EINPUT */
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	u32 emc_einput;
273
	/* Specifies the value for EMC_EINPUT_DURATION */
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	u32 emc_einput_duration;
275
	/* Specifies the value for EMC_PUTERM_EXTRA */
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	u32 emc_puterm_extra;
277
	/* Specifies the value for EMC_PUTERM_WIDTH */
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	u32 emc_puterm_width;
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280
	u32 emc_qrst;
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	u32 emc_qsafe;
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	u32 emc_rdv;
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	u32 emc_rdv_mask;
284

285
	u32 emc_rdv_early;
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	u32 emc_rdv_early_mask;
287

288
	/* Specifies the value for EMC_QPOP */
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	u32 emc_qpop;
290

291
	/* Specifies the value for EMC_REFRESH */
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	u32 emc_refresh;
293
	/* Specifies the value for EMC_BURST_REFRESH_NUM */
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	u32 emc_burst_refresh_num;
295
	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
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	u32 emc_prerefresh_req_cnt;
297
	/* Specifies the value for EMC_PDEX2WR */
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	u32 emc_pdex2wr;
299
	/* Specifies the value for EMC_PDEX2RD */
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	u32 emc_pdex2rd;
301
	/* Specifies the value for EMC_PCHG2PDEN */
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	u32 emc_pchg2pden;
303
	/* Specifies the value for EMC_ACT2PDEN */
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	u32 emc_act2pden;
305
	/* Specifies the value for EMC_AR2PDEN */
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	u32 emc_ar2pden;
307
	/* Specifies the value for EMC_RW2PDEN */
308
	u32 emc_rw2pden;
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310
	u32 emc_cke2pden;
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	u32 emc_pdex2che;
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	u32 emc_pdex2mrr;
313

314
	/* Specifies the value for EMC_TXSR */
315
	u32 emc_txsr;
316
	/* Specifies the value for EMC_TXSRDLL */
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	u32 emc_txsr_dll;
318
	/* Specifies the value for EMC_TCKE */
319
	u32 emc_tcke;
320
	/* Specifies the value for EMC_TCKESR */
321
	u32 emc_tckesr;
322
	/* Specifies the value for EMC_TPD */
323
	u32 emc_tpd;
324
	/* Specifies the value for EMC_TFAW */
325
	u32 emc_tfaw;
326
	/* Specifies the value for EMC_TRPAB */
327
	u32 emc_trpab;
328
	/* Specifies the value for EMC_TCLKSTABLE */
329
	u32 emc_tclkstable;
330
	/* Specifies the value for EMC_TCLKSTOP */
331
	u32 emc_tclkstop;
332
	/* Specifies the value for EMC_TREFBW */
333
	u32 emc_trefbw;
334

335
	/* FBIO configuration values */
336

337
	/* Specifies the value for EMC_FBIO_CFG5 */
338
	u32 emc_fbio_cfg5;
339
	/* Specifies the value for EMC_FBIO_CFG7 */
340
	u32 emc_fbio_cfg7;
341
	u32 emc_fbio_cfg8;
342

343
	/* Command mapping for CMD brick 0 */
344
	u32 emc_cmd_mapping_cmd0_0;
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	u32 emc_cmd_mapping_cmd0_1;
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	u32 emc_cmd_mapping_cmd0_2;
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	u32 emc_cmd_mapping_cmd1_0;
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	u32 emc_cmd_mapping_cmd1_1;
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	u32 emc_cmd_mapping_cmd1_2;
350
	u32 emc_cmd_mapping_cmd2_0;
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	u32 emc_cmd_mapping_cmd2_1;
352
	u32 emc_cmd_mapping_cmd2_2;
353
	u32 emc_cmd_mapping_cmd3_0;
354
	u32 emc_cmd_mapping_cmd3_1;
355
	u32 emc_cmd_mapping_cmd3_2;
356
	u32 emc_cmd_mapping_byte;
357

358
	/* Specifies the value for EMC_FBIO_SPARE */
359
	u32 emc_fbio_spare;
360

361
	/* Specifies the value for EMC_CFG_RSV */
362
	u32 emc_cfg_rsv;
363

364
	/* MRS command values */
365

366
	/* Specifies the value for EMC_MRS */
367
	u32 emc_mrs;
368
	/* Specifies the MP0 command to initialize mode registers */
369
	u32 emc_emrs;
370
	/* Specifies the MP2 command to initialize mode registers */
371
	u32 emc_emrs2;
372
	/* Specifies the MP3 command to initialize mode registers */
373
	u32 emc_emrs3;
374
	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
375
	u32 emc_mrw1;
376
	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
377
	u32 emc_mrw2;
378
	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
379
	u32 emc_mrw3;
380
	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
381
	u32 emc_mrw4;
382

383
	/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
384
	u32 emc_mrw6;
385
	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
386
	u32 emc_mrw8;
387
	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
388
	u32 emc_mrw9;
389
	/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
390
	u32 emc_mrw10;
391
	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
392
	u32 emc_mrw12;
393
	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
394
	u32 emc_mrw13;
395
	/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
396
	u32 emc_mrw14;
397

398
	/*
399
	 * Specifies the programming to extra LPDDR2 Mode Register
400
	 * at cold boot
401
	 */
402
	u32 emc_mrw_extra;
403
	/*
404
	 * Specifies the programming to extra LPDDR2 Mode Register
405
	 * at warm boot
406
	 */
407
	u32 emc_warm_boot_mrw_extra;
408
	/*
409
	 * Specify the enable of extra Mode Register programming at
410
	 * warm boot
411
	 */
412
	u32 emc_warm_boot_extramode_reg_write_enable;
413
	/*
414
	 * Specify the enable of extra Mode Register programming at
415
	 * cold boot
416
	 */
417
	u32 emc_extramode_reg_write_enable;
418

419
	/* Specifies the EMC_MRW reset command value */
420
	u32 emc_mrw_reset_command;
421
	/* Specifies the EMC Reset wait time (in microseconds) */
422
	u32 emc_mrw_reset_ninit_wait;
423
	/* Specifies the value for EMC_MRS_WAIT_CNT */
424
	u32 emc_mrs_wait_cnt;
425
	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
426
	u32 emc_mrs_wait_cnt2;
427

428
	/* EMC miscellaneous configurations */
429

430
	/* Specifies the value for EMC_CFG */
431
	u32 emc_cfg;
432
	/* Specifies the value for EMC_CFG_2 */
433
	u32 emc_cfg2;
434
	/* Specifies the pipe bypass controls */
435
	u32 emc_cfg_pipe;
436

437
	u32 emc_cfg_pipe_clk;
438
	u32 emc_fdpd_ctrl_cmd_no_ramp;
439
	u32 emc_cfg_update;
440

441
	/* Specifies the value for EMC_DBG */
442
	u32 emc_dbg;
443

444
	u32 emc_dbg_write_mux;
445

446
	/* Specifies the value for EMC_CMDQ */
447
	u32 emc_cmd_q;
448
	/* Specifies the value for EMC_MC2EMCQ */
449
	u32 emc_mc2emc_q;
450
	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
451
	u32 emc_dyn_self_ref_control;
452

453
	/* Specifies the value for MEM_INIT_DONE */
454
	u32 ahb_arbitration_xbar_ctrl_meminit_done;
455

456
	/* Specifies the value for EMC_CFG_DIG_DLL */
457
	u32 emc_cfg_dig_dll;
458
	u32 emc_cfg_dig_dll_1;
459

460
	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
461
	u32 emc_cfg_dig_dll_period;
462
	/* Specifies the value of *DEV_SELECTN of various EMC registers */
463
	u32 emc_dev_select;
464

465
	/* Specifies the value for EMC_SEL_DPD_CTRL */
466
	u32 emc_sel_dpd_ctrl;
467

468
	/* Pads trimmer delays */
469
	u32 emc_fdpd_ctrl_dq;
470
	u32 emc_fdpd_ctrl_cmd;
471
	u32 emc_pmacro_ib_vref_dq_0;
472
	u32 emc_pmacro_ib_vref_dq_1;
473
	u32 emc_pmacro_ib_vref_dqs_0;
474
	u32 emc_pmacro_ib_vref_dqs_1;
475
	u32 emc_pmacro_ib_rxrt;
476
	u32 emc_cfg_pipe1;
477
	u32 emc_cfg_pipe2;
478

479
	/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
480
	u32 emc_pmacro_quse_ddll_rank0_0;
481
	u32 emc_pmacro_quse_ddll_rank0_1;
482
	u32 emc_pmacro_quse_ddll_rank0_2;
483
	u32 emc_pmacro_quse_ddll_rank0_3;
484
	u32 emc_pmacro_quse_ddll_rank0_4;
485
	u32 emc_pmacro_quse_ddll_rank0_5;
486
	u32 emc_pmacro_quse_ddll_rank1_0;
487
	u32 emc_pmacro_quse_ddll_rank1_1;
488
	u32 emc_pmacro_quse_ddll_rank1_2;
489
	u32 emc_pmacro_quse_ddll_rank1_3;
490
	u32 emc_pmacro_quse_ddll_rank1_4;
491
	u32 emc_pmacro_quse_ddll_rank1_5;
492

493
	u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
494
	u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
495
	u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
496
	u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
497
	u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
498
	u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
499
	u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
500
	u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
501
	u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
502
	u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
503
	u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
504
	u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
505

506
	u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
507
	u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
508
	u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
509
	u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
510
	u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
511
	u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
512
	u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
513
	u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
514
	u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
515
	u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
516
	u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
517
	u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
518

519
	u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
520
	u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
521
	u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
522
	u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
523
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
524
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
525
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
526
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
527

528
	u32 emc_pmacro_ddll_long_cmd_0;
529
	u32 emc_pmacro_ddll_long_cmd_1;
530
	u32 emc_pmacro_ddll_long_cmd_2;
531
	u32 emc_pmacro_ddll_long_cmd_3;
532
	u32 emc_pmacro_ddll_long_cmd_4;
533
	u32 emc_pmacro_ddll_short_cmd_0;
534
	u32 emc_pmacro_ddll_short_cmd_1;
535
	u32 emc_pmacro_ddll_short_cmd_2;
536

537
	u32 emc_pmacro_ddll_periodic_offset;
538

539
	/*
540
	 * Specifies the delay after asserting CKE pin during a WarmBoot0
541
	 * sequence (in microseconds)
542
	 */
543
	u32 warm_boot_wait;
544

545
	/* Specifies the value for EMC_ODT_WRITE */
546
	u32 emc_odt_write;
547

548
	/* Periodic ZQ calibration */
549

550
	/*
551
	 * Specifies the value for EMC_ZCAL_INTERVAL
552
	 * Value 0 disables ZQ calibration
553
	 */
554
	u32 emc_zcal_interval;
555
	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
556
	u32 emc_zcal_wait_cnt;
557
	/* Specifies the value for EMC_ZCAL_MRW_CMD */
558
	u32 emc_zcal_mrw_cmd;
559

560
	/* DRAM initialization sequence flow control */
561

562
	/* Specifies the MRS command value for resetting DLL */
563
	u32 emc_mrs_reset_dll;
564
	/* Specifies the command for ZQ initialization of device 0 */
565
	u32 emc_zcal_init_dev0;
566
	/* Specifies the command for ZQ initialization of device 1 */
567
	u32 emc_zcal_init_dev1;
568
	/*
569
	 * Specifies the wait time after programming a ZQ initialization
570
	 * command (in microseconds)
571
	 */
572
	u32 emc_zcal_init_wait;
573
	/*
574
	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
575
	 * and warm boot [bit 1]
576
	 */
577
	u32 emc_zcal_warm_cold_boot_enables;
578

579
	/*
580
	 * Specifies the MRW command to LPDDR2 for ZQ calibration
581
	 * on warmboot
582
	 */
583
	/* Is issued to both devices separately */
584
	u32 emc_mrw_lpddr2zcal_warm_boot;
585
	/*
586
	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
587
	 * Is issued to both devices separately
588
	 */
589
	u32 emc_zqcal_ddr3_warm_boot;
590

591
	u32 emc_zqcal_lpddr4_warm_boot;
592

593
	/*
594
	 * Specifies the wait time for ZQ calibration on warmboot
595
	 * (in microseconds)
596
	 */
597
	u32 emc_zcal_warm_boot_wait;
598
	/*
599
	 * Specifies the enable for DRAM Mode Register programming
600
	 * at warm boot
601
	 */
602
	u32 emc_mrs_warm_boot_enable;
603
	/*
604
	 * Specifies the wait time after sending an MRS DLL reset command
605
	 * in microseconds)
606
	 */
607
	u32 emc_mrs_reset_dll_wait;
608
	/* Specifies the extra MRS command to initialize mode registers */
609
	u32 emc_mrs_extra;
610
	/* Specifies the extra MRS command at warm boot */
611
	u32 emc_warm_boot_mrs_extra;
612
	/* Specifies the EMRS command to enable the DDR2 DLL */
613
	u32 emc_emrs_ddr2_dll_enable;
614
	/* Specifies the MRS command to reset the DDR2 DLL */
615
	u32 emc_mrs_ddr2_dll_reset;
616
	/* Specifies the EMRS command to set OCD calibration */
617
	u32 emc_emrs_ddr2_ocd_calib;
618
	/*
619
	 * Specifies the wait between initializing DDR and setting OCD
620
	 * calibration (in microseconds)
621
	 */
622
	u32 emc_ddr2_wait;
623
	/* Specifies the value for EMC_CLKEN_OVERRIDE */
624
	u32 emc_clken_override;
625
	/*
626
	 * Specifies LOG2 of the extra refresh numbers after booting
627
	 * Program 0 to disable
628
	 */
629
	u32 emc_extra_refresh_num;
630
	/* Specifies the master override for all EMC clocks */
631
	u32 emc_clken_override_allwarm_boot;
632
	/* Specifies the master override for all MC clocks */
633
	u32 mc_clken_override_allwarm_boot;
634
	/* Specifies digital dll period, choosing between 4 to 64 ms */
635
	u32 emc_cfg_dig_dll_period_warm_boot;
636

637
	/* Pad controls */
638

639
	/* Specifies the value for PMC_VDDP_SEL */
640
	u32 pmc_vddp_sel;
641
	/* Specifies the wait time after programming PMC_VDDP_SEL */
642
	u32 pmc_vddp_sel_wait;
643
	/* Specifies the value for PMC_DDR_CFG */
644
	u32 pmc_ddr_cfg;
645
	/* Specifies the value for PMC_IO_DPD3_REQ */
646
	u32 pmc_io_dpd3_req;
647
	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
648
	u32 pmc_io_dpd3_req_wait;
649

650
	u32 pmc_io_dpd4_req_wait;
651

652
	/* Specifies the value for PMC_REG_SHORT */
653
	u32 pmc_reg_short;
654
	/* Specifies the value for PMC_NO_IOPOWER */
655
	u32 pmc_no_io_power;
656

657
	u32 pmc_ddr_ctrl_wait;
658
	u32 pmc_ddr_ctrl;
659

660
	/* Specifies the value for EMC_ACPD_CONTROL */
661
	u32 emc_acpd_control;
662

663
	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
664
	u32 emc_swizzle_rank0_byte0;
665
	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
666
	u32 emc_swizzle_rank0_byte1;
667
	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
668
	u32 emc_swizzle_rank0_byte2;
669
	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
670
	u32 emc_swizzle_rank0_byte3;
671
	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
672
	u32 emc_swizzle_rank1_byte0;
673
	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
674
	u32 emc_swizzle_rank1_byte1;
675
	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
676
	u32 emc_swizzle_rank1_byte2;
677
	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
678
	u32 emc_swizzle_rank1_byte3;
679

680
	/* Specifies the value for EMC_TXDSRVTTGEN */
681
	u32 emc_txdsrvttgen;
682

683
	/* Specifies the value for EMC_DATA_BRLSHFT_0 */
684
	u32 emc_data_brlshft0;
685
	u32 emc_data_brlshft1;
686

687
	u32 emc_dqs_brlshft0;
688
	u32 emc_dqs_brlshft1;
689

690
	u32 emc_cmd_brlshft0;
691
	u32 emc_cmd_brlshft1;
692
	u32 emc_cmd_brlshft2;
693
	u32 emc_cmd_brlshft3;
694

695
	u32 emc_quse_brlshft0;
696
	u32 emc_quse_brlshft1;
697
	u32 emc_quse_brlshft2;
698
	u32 emc_quse_brlshft3;
699

700
	u32 emc_dll_cfg0;
701
	u32 emc_dll_cfg1;
702

703
	u32 emc_pmc_scratch1;
704
	u32 emc_pmc_scratch2;
705
	u32 emc_pmc_scratch3;
706

707
	u32 emc_pmacro_pad_cfg_ctrl;
708

709
	u32 emc_pmacro_vttgen_ctrl0;
710
	u32 emc_pmacro_vttgen_ctrl1;
711
	u32 emc_pmacro_vttgen_ctrl2;
712
	u32 emc_pmacro_dsr_vttgen_ctrl0;
713
	u32 emc_pmacro_brick_ctrl_rfu1;
714
	u32 emc_pmacro_cmd_brick_ctrl_fdpd;
715
	u32 emc_pmacro_brick_ctrl_rfu2;
716
	u32 emc_pmacro_data_brick_ctrl_fdpd;
717
	u32 emc_pmacro_bg_bias_ctrl0;
718
	u32 emc_pmacro_data_pad_rx_ctrl;
719
	u32 emc_pmacro_cmd_pad_rx_ctrl;
720
	u32 emc_pmacro_data_rx_term_mode;
721
	u32 emc_pmacro_cmd_rx_term_mode;
722
	u32 emc_pmacro_data_pad_tx_ctrl;
723
	u32 emc_pmacro_cmd_pad_tx_ctrl;
724
	u32 emc_cfg3;
725

726
	u32 emc_pmacro_tx_pwrd0;
727
	u32 emc_pmacro_tx_pwrd1;
728
	u32 emc_pmacro_tx_pwrd2;
729
	u32 emc_pmacro_tx_pwrd3;
730
	u32 emc_pmacro_tx_pwrd4;
731
	u32 emc_pmacro_tx_pwrd5;
732

733
	u32 emc_config_sample_delay;
734

735
	u32 emc_pmacro_brick_mapping0;
736
	u32 emc_pmacro_brick_mapping1;
737
	u32 emc_pmacro_brick_mapping2;
738

739
	u32 emc_pmacro_tx_sel_clk_src0;
740
	u32 emc_pmacro_tx_sel_clk_src1;
741
	u32 emc_pmacro_tx_sel_clk_src2;
742
	u32 emc_pmacro_tx_sel_clk_src3;
743
	u32 emc_pmacro_tx_sel_clk_src4;
744
	u32 emc_pmacro_tx_sel_clk_src5;
745

746
	u32 emc_pmacro_perbit_fgcg_ctrl0;
747
	u32 emc_pmacro_perbit_fgcg_ctrl1;
748
	u32 emc_pmacro_perbit_fgcg_ctrl2;
749
	u32 emc_pmacro_perbit_fgcg_ctrl3;
750
	u32 emc_pmacro_perbit_fgcg_ctrl4;
751
	u32 emc_pmacro_perbit_fgcg_ctrl5;
752
	u32 emc_pmacro_perbit_rfu_ctrl0;
753
	u32 emc_pmacro_perbit_rfu_ctrl1;
754
	u32 emc_pmacro_perbit_rfu_ctrl2;
755
	u32 emc_pmacro_perbit_rfu_ctrl3;
756
	u32 emc_pmacro_perbit_rfu_ctrl4;
757
	u32 emc_pmacro_perbit_rfu_ctrl5;
758
	u32 emc_pmacro_perbit_rfu1_ctrl0;
759
	u32 emc_pmacro_perbit_rfu1_ctrl1;
760
	u32 emc_pmacro_perbit_rfu1_ctrl2;
761
	u32 emc_pmacro_perbit_rfu1_ctrl3;
762
	u32 emc_pmacro_perbit_rfu1_ctrl4;
763
	u32 emc_pmacro_perbit_rfu1_ctrl5;
764

765
	u32 emc_pmacro_data_pi_ctrl;
766
	u32 emc_pmacro_cmd_pi_ctrl;
767

768
	u32 emc_pmacro_ddll_bypass;
769

770
	u32 emc_pmacro_ddll_pwrd0;
771
	u32 emc_pmacro_ddll_pwrd1;
772
	u32 emc_pmacro_ddll_pwrd2;
773

774
	u32 emc_pmacro_cmd_ctrl0;
775
	u32 emc_pmacro_cmd_ctrl1;
776
	u32 emc_pmacro_cmd_ctrl2;
777

778
	/* DRAM size information */
779

780
	/* Specifies the value for MC_EMEM_ADR_CFG */
781
	u32 mc_emem_adr_cfg;
782
	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
783
	u32 mc_emem_adr_cfg_dev0;
784
	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
785
	u32 mc_emem_adr_cfg_dev1;
786

787
	u32 mc_emem_adr_cfg_channel_mask;
788

789
	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
790
	u32 mc_emem_adr_cfg_bank_mask0;
791
	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
792
	u32 mc_emem_adr_cfg_bank_mask1;
793
	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
794
	u32 mc_emem_adr_cfg_bank_mask2;
795

796
	/*
797
	 * Specifies the value for MC_EMEM_CFG which holds the external memory
798
	 * size (in KBytes)
799
	 */
800
	u32 mc_emem_cfg;
801

802
	/* MC arbitration configuration */
803

804
	/* Specifies the value for MC_EMEM_ARB_CFG */
805
	u32 mc_emem_arb_cfg;
806
	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
807
	u32 mc_emem_arb_outstanding_req;
808

809
	u32 emc_emem_arb_refpb_hp_ctrl;
810
	u32 emc_emem_arb_refpb_bank_ctrl;
811

812
	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
813
	u32 mc_emem_arb_timing_rcd;
814
	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
815
	u32 mc_emem_arb_timing_rp;
816
	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
817
	u32 mc_emem_arb_timing_rc;
818
	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
819
	u32 mc_emem_arb_timing_ras;
820
	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
821
	u32 mc_emem_arb_timing_faw;
822
	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
823
	u32 mc_emem_arb_timing_rrd;
824
	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
825
	u32 mc_emem_arb_timing_rap2pre;
826
	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
827
	u32 mc_emem_arb_timing_wap2pre;
828
	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
829
	u32 mc_emem_arb_timing_r2r;
830
	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
831
	u32 mc_emem_arb_timing_w2w;
832
	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
833
	u32 mc_emem_arb_timing_r2w;
834
	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
835
	u32 mc_emem_arb_timing_w2r;
836

837
	u32 mc_emem_arb_timing_rfcpb;
838

839
	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
840
	u32 mc_emem_arb_da_turns;
841
	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
842
	u32 mc_emem_arb_da_covers;
843
	/* Specifies the value for MC_EMEM_ARB_MISC0 */
844
	u32 mc_emem_arb_misc0;
845
	/* Specifies the value for MC_EMEM_ARB_MISC1 */
846
	u32 mc_emem_arb_misc1;
847
	u32 mc_emem_arb_misc2;
848

849
	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
850
	u32 mc_emem_arb_ring1_throttle;
851
	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
852
	u32 mc_emem_arb_override;
853
	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
854
	u32 mc_emem_arb_override1;
855
	/* Specifies the value for MC_EMEM_ARB_RSV */
856
	u32 mc_emem_arb_rsv;
857

858
	u32 mc_da_cfg0;
859
	u32 mc_emem_arb_timing_ccdmw;
860

861
	/* Specifies the value for MC_CLKEN_OVERRIDE */
862
	u32 mc_clken_override;
863

864
	/* Specifies the value for MC_STAT_CONTROL */
865
	u32 mc_stat_control;
866
	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
867
	u32 mc_video_protect_bom;
868
	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
869
	u32 mc_video_protect_bom_adr_hi;
870
	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
871
	u32 mc_video_protect_size_mb;
872
	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
873
	u32 mc_video_protect_vpr_override;
874
	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
875
	u32 mc_video_protect_vpr_override1;
876
	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
877
	u32 mc_video_protect_gpu_override0;
878
	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
879
	u32 mc_video_protect_gpu_override1;
880
	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
881
	u32 mc_sec_carveout_bom;
882
	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
883
	u32 mc_sec_carveout_adr_hi;
884
	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
885
	u32 mc_sec_carveout_size_mb;
886
	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
887
	u32 mc_video_protect_write_access;
888
	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
889
	u32 mc_sec_carveout_protect_write_access;
890

891
	u32 mc_generalized_carveout1_bom;
892
	u32 mc_generalized_carveout1_bom_hi;
893
	u32 mc_generalized_carveout1_size_128kb;
894
	u32 mc_generalized_carveout1_access0;
895
	u32 mc_generalized_carveout1_access1;
896
	u32 mc_generalized_carveout1_access2;
897
	u32 mc_generalized_carveout1_access3;
898
	u32 mc_generalized_carveout1_access4;
899
	u32 mc_generalized_carveout1_force_internal_access0;
900
	u32 mc_generalized_carveout1_force_internal_access1;
901
	u32 mc_generalized_carveout1_force_internal_access2;
902
	u32 mc_generalized_carveout1_force_internal_access3;
903
	u32 mc_generalized_carveout1_force_internal_access4;
904
	u32 mc_generalized_carveout1_cfg0;
905

906
	u32 mc_generalized_carveout2_bom;
907
	u32 mc_generalized_carveout2_bom_hi;
908
	u32 mc_generalized_carveout2_size_128kb;
909
	u32 mc_generalized_carveout2_access0;
910
	u32 mc_generalized_carveout2_access1;
911
	u32 mc_generalized_carveout2_access2;
912
	u32 mc_generalized_carveout2_access3;
913
	u32 mc_generalized_carveout2_access4;
914
	u32 mc_generalized_carveout2_force_internal_access0;
915
	u32 mc_generalized_carveout2_force_internal_access1;
916
	u32 mc_generalized_carveout2_force_internal_access2;
917
	u32 mc_generalized_carveout2_force_internal_access3;
918
	u32 mc_generalized_carveout2_force_internal_access4;
919
	u32 mc_generalized_carveout2_cfg0;
920

921
	u32 mc_generalized_carveout3_bom;
922
	u32 mc_generalized_carveout3_bom_hi;
923
	u32 mc_generalized_carveout3_size_128kb;
924
	u32 mc_generalized_carveout3_access0;
925
	u32 mc_generalized_carveout3_access1;
926
	u32 mc_generalized_carveout3_access2;
927
	u32 mc_generalized_carveout3_access3;
928
	u32 mc_generalized_carveout3_access4;
929
	u32 mc_generalized_carveout3_force_internal_access0;
930
	u32 mc_generalized_carveout3_force_internal_access1;
931
	u32 mc_generalized_carveout3_force_internal_access2;
932
	u32 mc_generalized_carveout3_force_internal_access3;
933
	u32 mc_generalized_carveout3_force_internal_access4;
934
	u32 mc_generalized_carveout3_cfg0;
935

936
	u32 mc_generalized_carveout4_bom;
937
	u32 mc_generalized_carveout4_bom_hi;
938
	u32 mc_generalized_carveout4_size_128kb;
939
	u32 mc_generalized_carveout4_access0;
940
	u32 mc_generalized_carveout4_access1;
941
	u32 mc_generalized_carveout4_access2;
942
	u32 mc_generalized_carveout4_access3;
943
	u32 mc_generalized_carveout4_access4;
944
	u32 mc_generalized_carveout4_force_internal_access0;
945
	u32 mc_generalized_carveout4_force_internal_access1;
946
	u32 mc_generalized_carveout4_force_internal_access2;
947
	u32 mc_generalized_carveout4_force_internal_access3;
948
	u32 mc_generalized_carveout4_force_internal_access4;
949
	u32 mc_generalized_carveout4_cfg0;
950

951
	u32 mc_generalized_carveout5_bom;
952
	u32 mc_generalized_carveout5_bom_hi;
953
	u32 mc_generalized_carveout5_size_128kb;
954
	u32 mc_generalized_carveout5_access0;
955
	u32 mc_generalized_carveout5_access1;
956
	u32 mc_generalized_carveout5_access2;
957
	u32 mc_generalized_carveout5_access3;
958
	u32 mc_generalized_carveout5_access4;
959
	u32 mc_generalized_carveout5_force_internal_access0;
960
	u32 mc_generalized_carveout5_force_internal_access1;
961
	u32 mc_generalized_carveout5_force_internal_access2;
962
	u32 mc_generalized_carveout5_force_internal_access3;
963
	u32 mc_generalized_carveout5_force_internal_access4;
964
	u32 mc_generalized_carveout5_cfg0;
965

966
	/* Specifies enable for CA training */
967
	u32 emc_ca_training_enable;
968
	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
969
	u32 swizzle_rank_byte_encode;
970
	/* Specifies enable and offset for patched boot rom write */
971
	u32 boot_rom_patch_control;
972
	/* Specifies data for patched boot rom write */
973
	u32 boot_rom_patch_data;
974

975
	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
976
	u32 mc_mts_carveout_bom;
977
	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
978
	u32 mc_mts_carveout_adr_hi;
979
	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
980
	u32 mc_mts_carveout_size_mb;
981
	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
982
	u32 mc_mts_carveout_reg_ctrl;
983

984
	/* Specifies the clients that are allowed to access untranslated memory */
985
	u32 mc_untranslated_region_check;
986

987
	/* Just a place holder for special usage when there is no BCT for certain registers */
988
	u32 bct_na;
989
};
990

991
#endif
992

993