Path: blob/master/modules/hekate_libsys_minerva/mtc_mc_emc_regs.h
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/*1* Minerva Training Cell2* DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.3*4* Copyright (c) 2018 CTCaer <[email protected]>5*6* This program is free software; you can redistribute it and/or modify it7* under the terms and conditions of the GNU General Public License,8* version 2, as published by the Free Software Foundation.9*10* This program is distributed in the hope it will be useful, but WITHOUT11* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or12* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for13* more details.14*15* You should have received a copy of the GNU General Public License16* along with this program. If not, see <http://www.gnu.org/licenses/>.17*/1819#ifndef _MTC_MC_EMC_REGS_H_20#define _MTC_MC_EMC_REGS_H_2122/* Clock controller registers */23#define CLK_RST_CONTROLLER_PLLM_BASE 0x9024#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C25#define PLLM_ENABLE (1 << 30)26#define PLLM_LOCK (1 << 27)27#define PLLM_EN_LCKDET (1 << 4)2829#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C30#define EMC_2X_CLK_SRC_SHIFT 293132#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x28033#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x28434#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x28835#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E836#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x66437#define EMC_DLL_PLLM_VCOB (1 << 10)38#define EMC_DLL_SWITCH_OUT (1 << 11)3940#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE 0x7244142/* Memory controller registers */43#define MC_EMEM_ADR_CFG 0x5444#define MC_EMEM_ARB_CFG 0x9045#define MC_EMEM_ARB_OUTSTANDING_REQ 0x9446#define MC_EMEM_ARB_TIMING_RCD 0x9847#define MC_EMEM_ARB_TIMING_RP 0x9C48#define MC_EMEM_ARB_TIMING_RC 0xA049#define MC_EMEM_ARB_TIMING_RAS 0xA450#define MC_EMEM_ARB_TIMING_FAW 0xA851#define MC_EMEM_ARB_TIMING_RRD 0xAC52#define MC_EMEM_ARB_TIMING_RAP2PRE 0xB053#define MC_EMEM_ARB_TIMING_WAP2PRE 0xB454#define MC_EMEM_ARB_TIMING_R2R 0xB855#define MC_EMEM_ARB_TIMING_W2W 0xBC56#define MC_EMEM_ARB_TIMING_R2W 0xC057#define MC_EMEM_ARB_TIMING_W2R 0xC458#define MC_EMEM_ARB_MISC2 0xC859#define MC_EMEM_ARB_DA_TURNS 0xD060#define MC_EMEM_ARB_DA_COVERS 0xD461#define MC_EMEM_ARB_MISC0 0xD862#define MC_EMEM_ARB_MISC1 0xDC63#define MC_EMEM_ARB_RING1_THROTTLE 0xE06465#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E466#define MC_LATENCY_ALLOWANCE_HC_0 0x31067#define MC_LATENCY_ALLOWANCE_HC_1 0x31468#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x32069#define MC_LATENCY_ALLOWANCE_NVENC_0 0x32870#define MC_LATENCY_ALLOWANCE_PPCS_0 0x34471#define MC_LATENCY_ALLOWANCE_PPCS_1 0x34872#define MC_LATENCY_ALLOWANCE_ISP2_0 0x37073#define MC_LATENCY_ALLOWANCE_ISP2_1 0x37474#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C75#define MC_LATENCY_ALLOWANCE_XUSB_1 0x38076#define MC_LATENCY_ALLOWANCE_TSEC_0 0x39077#define MC_LATENCY_ALLOWANCE_VIC_0 0x39478#define MC_LATENCY_ALLOWANCE_VI2_0 0x39879#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC80#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B881#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC82#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C083#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C484#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D885#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E88687#define MC_MLL_MPCORER_PTSA_RATE 0x44C88#define MC_FTOP_PTSA_RATE 0x50C8990#define MC_EMEM_ARB_TIMING_RFCPB 0x6C091#define MC_EMEM_ARB_TIMING_CCDMW 0x6C492#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6F093#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6F49495#define MC_PTSA_GRANT_DECREMENT 0x9609697#define MC_EMEM_ARB_DHYST_CTRL 0xBCC98#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD099#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4100#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8101#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC102#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0103#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4104#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8105#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC106107/* External Memory controller registers */108#define EMC_INTSTATUS 0x0109#define CLKCHANGE_COMPLETE_INT (1 << 4)110111#define EMC_DBG 0x8112#define EMC_CFG 0xC113#define EMC_PIN 0x24114#define EMC_TIMING_CONTROL 0x28115#define EMC_RC 0x2C116#define EMC_RFC 0x30117#define EMC_RAS 0x34118#define EMC_RP 0x38119#define EMC_R2W 0x3C120#define EMC_W2R 0x40121#define EMC_R2P 0x44122#define EMC_W2P 0x48123#define EMC_RD_RCD 0x4C124#define EMC_WR_RCD 0x50125#define EMC_RRD 0x54126#define EMC_REXT 0x58127#define EMC_WDV 0x5C128#define EMC_QUSE 0x60129#define EMC_QRST 0x64130#define EMC_QSAFE 0x68131#define EMC_RDV 0x6C132#define EMC_REFRESH 0x70133#define EMC_BURST_REFRESH_NUM 0x74134#define EMC_PDEX2WR 0x78135#define EMC_PDEX2RD 0x7C136#define EMC_PCHG2PDEN 0x80137#define EMC_ACT2PDEN 0x84138#define EMC_AR2PDEN 0x88139#define EMC_RW2PDEN 0x8C140#define EMC_TXSR 0x90141#define EMC_TCKE 0x94142#define EMC_TFAW 0x98143#define EMC_TRPAB 0x9C144#define EMC_TCLKSTABLE 0xA0145#define EMC_TCLKSTOP 0xA4146#define EMC_TREFBW 0xA8147#define EMC_TPPD 0xAC148#define EMC_ODT_WRITE 0xB0149#define EMC_PDEX2MRR 0xB4150#define EMC_WEXT 0xB8151#define EMC_RFC_SLR 0xC0152#define EMC_MRS_WAIT_CNT2 0xC4153#define EMC_MRS_WAIT_CNT 0xC8154#define EMC_MRS 0xCC155#define EMC_EMRS 0xD0156#define EMC_REF 0xD4157#define EMC_MRW 0xE8158#define EMC_SELF_REF 0xE0159#define EMC_MRR 0xEC160#define EMC_FBIO_SPARE 0x100161#define EMC_FBIO_CFG5 0x104162#define EMC_PDEX2CKE 0x118163#define EMC_CKE2PDEN 0x11C164#define EMC_MPC 0x128165#define EMC_EMRS2 0x12C166#define EMC_MRW2 0x134167#define EMC_MRW3 0x138168#define EMC_MRW4 0x13C169#define EMC_R2R 0x144170#define EMC_EINPUT 0x14C171#define EMC_EINPUT_DURATION 0x150172#define EMC_PUTERM_EXTRA 0x154173#define EMC_TCKESR 0x158174#define EMC_TPD 0x15C175#define EMC_AUTO_CAL_CONFIG 0x2A4176177#define EMC_EMC_STATUS 0x2B4178#define TIMING_UPDATE_STALLED (1 << 23)179#define MRR_DIVLD (1 << 20)180#define IN_SELF_REFRESH_MASK (3 << 8)181#define IN_POWERDOWN_BOTH_MASK (3 << 4)182#define IN_POWERDOWN_1DEV_MASK (1 << 4)183#define REQ_FIFO_EMPTY (1 << 0)184185#define EMC_CFG_2 0x2B8186#define EMC_CFG_DIG_DLL 0x2BC187#define EMC_CFG_DIG_DLL_PERIOD 0x2C0188#define EMC_DIG_DLL_STATUS 0x2C4189#define EMC_RDV_MASK 0x2CC190#define EMC_WDV_MASK 0x2D0191#define EMC_RDV_EARLY_MASK 0x2D4192#define EMC_RDV_EARLY 0x2D8193#define EMC_AUTO_CAL_CONFIG8 0x2DC194#define EMC_ZCAL_INTERVAL 0x2E0195#define EMC_ZCAL_WAIT_CNT 0x2E4196#define EMC_ZQ_CAL 0x2EC197#define EMC_FDPD_CTRL_DQ 0x310198#define EMC_FDPD_CTRL_CMD 0x314199#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318200#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31C201#define EMC_SCRATCH0 0x324202#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330203#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334204#define EMC_TR_TIMING_0 0x3B4205#define EMC_TR_CTRL_0 0x3B8206#define EMC_TR_CTRL_1 0x3BC207#define EMC_SWITCH_BACK_CTRL 0x3C0208#define EMC_TR_RDV 0x3C4209#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3CC210#define EMC_SEL_DPD_CTRL 0x3D8211#define EMC_PRE_REFRESH_REQ_CNT 0x3DC212#define EMC_DYN_SELF_REF_CONTROL 0x3E0213#define EMC_TXSRDLL 0x3E4214#define EMC_CCFIFO_ADDR 0x3E8215#define EMC_CCFIFO_DATA 0x3EC216#define EMC_CCFIFO_STATUS 0x3F0217#define EMC_TR_QPOP 0x3F4218#define EMC_TR_RDV_MASK 0x3F8219#define EMC_TR_QSAFE 0x3FC220#define EMC_TR_QRST 0x400221#define EMC_AUTO_CAL_CONFIG2 0x458222#define EMC_AUTO_CAL_CONFIG3 0x45C223#define EMC_TR_DVFS 0x460224#define EMC_AUTO_CAL_CHANNEL 0x464225#define EMC_IBDLY 0x468226#define EMC_OBDLY 0x46c227#define EMC_TXDSRVTTGEN 0x480228#define EMC_WE_DURATION 0x48C229#define EMC_WS_DURATION 0x490230#define EMC_WEV 0x494231#define EMC_WSV 0x498232#define EMC_CFG_3 0x49C233#define EMC_MRW6 0x4A4234#define EMC_MRW7 0x4A8235#define EMC_MRW8 0x4AC236#define EMC_MRW14 0x4C4237#define EMC_MRW15 0x4D0238#define EMC_CFG_SYNC 0x4D4239#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4D8240#define EMC_WDV_CHK 0x4E0241#define EMC_CFG_PIPE_2 0x554242#define EMC_CFG_PIPE_CLK 0x558243#define EMC_CFG_PIPE_1 0x55C244#define EMC_CFG_PIPE 0x560245#define EMC_QPOP 0x564246#define EMC_QUSE_WIDTH 0x568247#define EMC_PUTERM_WIDTH 0x56C248#define EMC_AUTO_CAL_CONFIG7 0x574249#define EMC_REFCTRL2 0x580250#define EMC_FBIO_CFG7 0x584251252#define EMC_DATA_BRLSHFT_0 0x588253#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0254#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3255#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6256#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9257#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12258#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15259#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18260#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21261262#define EMC_DATA_BRLSHFT_1 0x58C263#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0264#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3265#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6266#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9267#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12268#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15269#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18270#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21271272#define EMC_RFCPB 0x590273#define EMC_DQS_BRLSHFT_0 0x594274#define EMC_DQS_BRLSHFT_1 0x598275#define EMC_CMD_BRLSHFT_0 0x59C276#define EMC_CMD_BRLSHFT_1 0x5A0277#define EMC_CMD_BRLSHFT_2 0x5A4278#define EMC_CMD_BRLSHFT_3 0x5A8279#define EMC_QUSE_BRLSHFT_0 0x5AC280#define EMC_AUTO_CAL_CONFIG4 0x5B0281#define EMC_AUTO_CAL_CONFIG5 0x5B4282#define EMC_QUSE_BRLSHFT_1 0x5B8283#define EMC_QUSE_BRLSHFT_2 0x5BC284#define EMC_CCDMW 0x5C0285#define EMC_QUSE_BRLSHFT_3 0x5C4286#define EMC_AUTO_CAL_CONFIG6 0x5CC287#define EMC_DLL_CFG_0 0x5E4288#define EMC_DLL_CFG_1 0x5E8289#define EMC_CONFIG_SAMPLE_DELAY 0x5F0290#define EMC_CFG_UPDATE 0x5F4291292#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600293#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604294#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608295#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60C296#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610297#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614298#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630299#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634300#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620301#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624302#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628303#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62C304305#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640306#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644307#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648308#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64C309#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650310#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654311#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660312#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664313#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668314#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66C315#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670316#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674317318#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680319#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684320#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688321#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68C322#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690323#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694324#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6A0325#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6A4326#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6A8327#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6AC328#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6B0329#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6B4330331#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6C0332#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6C4333#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6C8334#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6CC335#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6E0336#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6E4337#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6E8338#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6EC339340#define EMC_PMACRO_TX_PWRD_0 0x720341#define EMC_PMACRO_TX_PWRD_1 0x724342#define EMC_PMACRO_TX_PWRD_2 0x728343#define EMC_PMACRO_TX_PWRD_3 0x72C344#define EMC_PMACRO_TX_PWRD_4 0x730345#define EMC_PMACRO_TX_PWRD_5 0x734346347#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740348#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744349#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74C350#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748351#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750352#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754353354#define EMC_PMACRO_DDLL_BYPASS 0x760355#define EMC_PMACRO_DDLL_PWRD_0 0x770356#define EMC_PMACRO_DDLL_PWRD_1 0x774357#define EMC_PMACRO_DDLL_PWRD_2 0x778358359#define EMC_PMACRO_CMD_CTRL_0 0x780360#define EMC_PMACRO_CMD_CTRL_1 0x784361#define EMC_PMACRO_CMD_CTRL_2 0x788362363#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800364#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804365#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808366#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80C367#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810368#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814369#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818370#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81C371#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820372#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824373#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828374#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82C375#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830376#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834377#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838378#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83C379#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840380#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844381#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848382#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84C383#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850384#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854385#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858386#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85C387#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860388#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864389#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868390#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86C391#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870392#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874393#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878394#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87C395396#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880397#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884398#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888399#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88C400#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890401#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894402#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898403#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89C404#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8A0405#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8A4406#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8A8407#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8AC408#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8B0409#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8B4410#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8B8411#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8BC412413#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900414#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904415#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908416#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90C417#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910418#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914419#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918420#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91C421#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920422#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924423#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928424#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92C425#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930426#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934427#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938428#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93C429#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940430#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944431#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948432#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94C433#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950434#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954435#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958436#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95C437#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960438#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964439#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968440#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96C441#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970442#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974443#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978444#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97C445446#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980447#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984448#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988449#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98C450#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990451#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994452#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998453#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99C454#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9A0455#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9A4456#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9A8457#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9AC458#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9B0459#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9B4460#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9B8461#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9BC462463#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xA00464#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xA04465#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xA08466#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xA10467#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xA14468#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xA18469#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xA20470#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xA24471#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xA28472#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xA30473#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xA34474#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xA38475#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xA40476#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xA44477#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xA48478#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xA50479#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xA54480#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xA58481#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xA60482#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xA64483#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xA68484#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xA70485#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xA74486#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xA78487488#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xB00489#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xB04490#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xB08491#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xB10492#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xB14493#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xB18494#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xB20495#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xB24496#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xB28497#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xB30498#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xB34499#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xB38500#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xB40501#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xB44502#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xB48503#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xB50504#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xB54505#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xB58506#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xB60507#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xB64508#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xB68509#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xB70510#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xB74511#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xB78512513#define EMC_PMACRO_IB_VREF_DQ_0 0xBE0514#define EMC_PMACRO_IB_VREF_DQ_1 0xBE4515#define EMC_PMACRO_IB_VREF_DQS_0 0xBF0516#define EMC_PMACRO_IB_VREF_DQS_1 0xBF4517518#define EMC_PMACRO_DDLL_LONG_CMD_0 0xC00519#define EMC_PMACRO_DDLL_LONG_CMD_1 0xC04520#define EMC_PMACRO_DDLL_LONG_CMD_2 0xC08521#define EMC_PMACRO_DDLL_LONG_CMD_3 0xC0C522#define EMC_PMACRO_DDLL_LONG_CMD_4 0xC10523524#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xC20525#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xC24526#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xC28527528#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xC30529#define EMC_PMACRO_VTTGEN_CTRL_0 0xC34530#define EMC_PMACRO_VTTGEN_CTRL_1 0xC38531#define EMC_PMACRO_BG_BIAS_CTRL_0 0xC3C532#define EMC_PMACRO_PAD_CFG_CTRL 0xC40533#define EMC_PMACRO_ZCTRL 0xC44534#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xC50535#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xC54536#define EMC_PMACRO_CMD_RX_TERM_MODE 0xC58537#define EMC_PMACRO_DATA_RX_TERM_MODE 0xC5C538#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xC60539#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xC64540#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xC68541#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xC78542#define EMC_PMACRO_VTTGEN_CTRL_2 0xCF0543#define EMC_PMACRO_IB_RXRT 0xCF4544#define EMC_PMACRO_TRAINING_CTRL_0 0xCF8545#define CH0_TRAINING_E_WRPTR (1 << 3)546#define EMC_PMACRO_TRAINING_CTRL_1 0xCFC547548#define EMC_TRAINING_CMD 0xE00549#define EMC_TRAINING_CTRL 0xE04550#define EMC_TRAINING_STATUS 0xE08551#define EMC_TRAINING_QUSE_CORS_CTRL 0xE0C552#define EMC_TRAINING_QUSE_FINE_CTRL 0xE10553#define EMC_TRAINING_QUSE_CTRL_MISC 0xE14554#define EMC_TRAINING_WRITE_FINE_CTRL 0xE18555#define EMC_TRAINING_WRITE_CTRL_MISC 0xE1C556#define EMC_TRAINING_WRITE_VREF_CTRL 0xE20557#define EMC_TRAINING_READ_FINE_CTRL 0xE24558#define EMC_TRAINING_READ_CTRL_MISC 0xE28559#define EMC_TRAINING_READ_VREF_CTRL 0xE2C560#define EMC_TRAINING_CA_FINE_CTRL 0xE30561#define EMC_TRAINING_CA_CTRL_MISC 0xE34562#define EMC_TRAINING_CA_CTRL_MISC1 0xE38563#define EMC_TRAINING_CA_VREF_CTRL 0xE3C564#define EMC_TRAINING_SETTLE 0xE44565#define EMC_TRAINING_MPC 0xE5C566#define EMC_TRAINING_PATRAM_CTRL 0xE60567#define EMC_TRAINING_PATRAM_DQ 0xE64568#define EMC_TRAINING_PATRAM_DMI 0xE68569#define EMC_TRAINING_VREF_SETTLE 0xE6C570#define EMC_TRAINING_OPT_CA_VREF 0xEC0571#define EMC_TRAINING_OPT_DQ_OB_VREF 0xEC4572#define EMC_TRAINING_QUSE_VREF_CTRL 0xED0573#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xED4574#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xED8575576/* Per channel registers offsets. Should be used with EMC_BASE */577#define EMC0_MRW10 0x34B4578#define EMC0_MRW11 0x34B8579#define EMC0_MRW12 0x34BC580#define EMC0_MRW13 0x34C0581#define EMC0_DATA_BRLSHFT_0 0x3588582#define EMC0_DATA_BRLSHFT_1 0x358C583#define EMC0_CMD_BRLSHFT_0 0x359C584#define EMC0_QUSE_BRLSHFT_0 0x35AC585#define EMC0_QUSE_BRLSHFT_2 0x35BC586#define EMC0_TRAINING_RW_OFFSET_IB_BYTE0 0x3E98587#define EMC0_TRAINING_RW_OFFSET_IB_BYTE1 0x3E9C588#define EMC0_TRAINING_RW_OFFSET_IB_BYTE2 0x3EA0589#define EMC0_TRAINING_RW_OFFSET_IB_BYTE3 0x3EA4590#define EMC0_TRAINING_RW_OFFSET_IB_MISC 0x3EA8591#define EMC0_TRAINING_RW_OFFSET_OB_BYTE0 0x3EAC592#define EMC0_TRAINING_RW_OFFSET_OB_BYTE1 0x3EB0593#define EMC0_TRAINING_RW_OFFSET_OB_BYTE2 0x3EB4594#define EMC0_TRAINING_RW_OFFSET_OB_BYTE3 0x3EB8595#define EMC0_TRAINING_RW_OFFSET_OB_MISC 0x3EBC596#define EMC0_TRAINING_OPT_DQS_IB_VREF_RANK0 0x3ED4597#define EMC0_TRAINING_OPT_DQS_IB_VREF_RANK1 0x3ED8598599#define EMC1_MRW10 0x44B4600#define EMC1_MRW11 0x44B8601#define EMC1_MRW12 0x44BC602#define EMC1_MRW13 0x44C0603#define EMC1_DATA_BRLSHFT_0 0x4588604#define EMC1_DATA_BRLSHFT_1 0x458C605#define EMC1_CMD_BRLSHFT_1 0x45A0606#define EMC1_QUSE_BRLSHFT_1 0x45B8607#define EMC1_QUSE_BRLSHFT_3 0x45C4608#define EMC1_TRAINING_RW_OFFSET_IB_BYTE0 0x4E98609#define EMC1_TRAINING_RW_OFFSET_IB_BYTE1 0x4E9C610#define EMC1_TRAINING_RW_OFFSET_IB_BYTE2 0x4EA0611#define EMC1_TRAINING_RW_OFFSET_IB_BYTE3 0x4EA4612#define EMC1_TRAINING_RW_OFFSET_IB_MISC 0x4EA8613#define EMC1_TRAINING_RW_OFFSET_OB_BYTE0 0x4EAC614#define EMC1_TRAINING_RW_OFFSET_OB_BYTE1 0x4EB0615#define EMC1_TRAINING_RW_OFFSET_OB_BYTE2 0x4EB4616#define EMC1_TRAINING_RW_OFFSET_OB_BYTE3 0x4EB8617#define EMC1_TRAINING_RW_OFFSET_OB_MISC 0x4EBC618#define EMC1_TRAINING_OPT_DQS_IB_VREF_RANK0 0x4ED4619#define EMC1_TRAINING_OPT_DQS_IB_VREF_RANK1 0x4ED8620621#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE0_SHIFT 0622#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE1_SHIFT 16623#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE2_SHIFT 0624#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE3_SHIFT 16625#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE4_SHIFT 0626#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE5_SHIFT 16627#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE6_SHIFT 0628#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE7_SHIFT 16629630#endif631632