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CTCaer
GitHub Repository: CTCaer/hekate
 Path: blob/master/modules/hekate_libsys_minerva/mtc_table.h
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1
/*

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 * Minerva Training Cell

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 * DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.

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 *

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 * Copyright (c) 2018 CTCaer  <[email protected]>

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

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 * version 2, as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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 * more details.

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 *

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 * You should have received a copy of the GNU General Public License

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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

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 */

19


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#ifndef _MTC_TABLE_H_

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#define _MTC_TABLE_H_

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#include "types.h"

24


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typedef struct

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{

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	u32 pll_osc_in;

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	u32 pll_out;

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	u32 pll_feedback_div;

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	u32 pll_input_div;

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	u32 pll_post_div;

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} pllm_clk_config_t;

33


34
typedef struct

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{

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	u32 emc_rc;

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	u32 emc_rfc;

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	u32 emc_rfcpb;

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	u32 emc_refctrl2;

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	u32 emc_rfc_slr;

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	u32 emc_ras;

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	u32 emc_rp;

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	u32 emc_r2w;

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	u32 emc_w2r;

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	u32 emc_r2p;

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	u32 emc_w2p;

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	u32 emc_r2r;

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	u32 emc_tppd;

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	u32 emc_ccdmw;

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	u32 emc_rd_rcd;

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	u32 emc_wr_rcd;

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	u32 emc_rrd;

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	u32 emc_rext;

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	u32 emc_wext;

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	u32 emc_wdv_chk;

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	u32 emc_wdv;

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	u32 emc_wsv;

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	u32 emc_wev;

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	u32 emc_wdv_mask;

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	u32 emc_ws_duration;

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	u32 emc_we_duration;

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	u32 emc_quse;

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	u32 emc_quse_width;

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	u32 emc_ibdly;

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	u32 emc_obdly;

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	u32 emc_einput;

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	u32 emc_mrw6;

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	u32 emc_einput_duration;

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	u32 emc_puterm_extra;

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	u32 emc_puterm_width;

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	u32 emc_qrst;

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	u32 emc_qsafe;

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	u32 emc_rdv;

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	u32 emc_rdv_mask;

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	u32 emc_rdv_early;

76
	u32 emc_rdv_early_mask;

77
	u32 emc_refresh;

78
	u32 emc_burst_refresh_num;

79
	u32 emc_pre_refresh_req_cnt;

80
	u32 emc_pdex2wr;

81
	u32 emc_pdex2rd;

82
	u32 emc_pchg2pden;

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	u32 emc_act2pden;

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	u32 emc_ar2pden;

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	u32 emc_rw2pden;

86
	u32 emc_cke2pden;

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	u32 emc_pdex2cke;

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	u32 emc_pdex2mrr;

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	u32 emc_txsr;

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	u32 emc_txsrdll;

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	u32 emc_tcke;

92
	u32 emc_tckesr;

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	u32 emc_tpd;

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	u32 emc_tfaw;

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	u32 emc_trpab;

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	u32 emc_tclkstable;

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	u32 emc_tclkstop;

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	u32 emc_mrw7;

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	u32 emc_trefbw;

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	u32 emc_odt_write;

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	u32 emc_fbio_cfg5;

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	u32 emc_fbio_cfg7;

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	u32 emc_cfg_dig_dll;

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	u32 emc_cfg_dig_dll_period;

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	u32 emc_pmacro_ib_rxrt;

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	u32 emc_cfg_pipe_1;

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	u32 emc_cfg_pipe_2;

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	u32 emc_pmacro_quse_ddll_rank0_4;

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	u32 emc_pmacro_quse_ddll_rank0_5;

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	u32 emc_pmacro_quse_ddll_rank1_4;

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	u32 emc_pmacro_quse_ddll_rank1_5;

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	u32 emc_mrw8;

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	u32 emc_pmacro_ob_ddll_long_dq_rank1_4;

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	u32 emc_pmacro_ob_ddll_long_dq_rank1_5;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;

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	u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;

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	u32 emc_pmacro_ddll_long_cmd_0;

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	u32 emc_pmacro_ddll_long_cmd_1;

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	u32 emc_pmacro_ddll_long_cmd_2;

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	u32 emc_pmacro_ddll_long_cmd_3;

131
	u32 emc_pmacro_ddll_long_cmd_4;

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	u32 emc_pmacro_ddll_short_cmd_0;

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	u32 emc_pmacro_ddll_short_cmd_1;

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	u32 emc_pmacro_ddll_short_cmd_2;

135
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;

137
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;

145
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;

149
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;

150
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;

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	u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;

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	u32 emc_txdsrvttgen;

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	u32 emc_fdpd_ctrl_dq;

173
	u32 emc_fdpd_ctrl_cmd;

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	u32 emc_fbio_spare;

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	u32 emc_zcal_interval;

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	u32 emc_zcal_wait_cnt;

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	u32 emc_mrs_wait_cnt;

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	u32 emc_mrs_wait_cnt2;

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	u32 emc_auto_cal_channel;

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	u32 emc_dll_cfg_0;

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	u32 emc_dll_cfg_1;

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	u32 emc_pmacro_autocal_cfg_common;

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	u32 emc_pmacro_zctrl;

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	u32 emc_cfg;

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	u32 emc_cfg_pipe;

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	u32 emc_dyn_self_ref_control;

187
	u32 emc_qpop;

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	u32 emc_dqs_brlshft_0;

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	u32 emc_dqs_brlshft_1;

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	u32 emc_cmd_brlshft_2;

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	u32 emc_cmd_brlshft_3;

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	u32 emc_pmacro_pad_cfg_ctrl;

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	u32 emc_pmacro_data_pad_rx_ctrl;

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	u32 emc_pmacro_cmd_pad_rx_ctrl;

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	u32 emc_pmacro_data_rx_term_mode;

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	u32 emc_pmacro_cmd_rx_term_mode;

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	u32 emc_pmacro_cmd_pad_tx_ctrl;

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	u32 emc_pmacro_data_pad_tx_ctrl;

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	u32 emc_pmacro_common_pad_tx_ctrl;

200
	u32 emc_pmacro_vttgen_ctrl_0;

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	u32 emc_pmacro_vttgen_ctrl_1;

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	u32 emc_pmacro_vttgen_ctrl_2;

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	u32 emc_pmacro_brick_ctrl_rfu1;

204
	u32 emc_pmacro_cmd_brick_ctrl_fdpd;

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	u32 emc_pmacro_brick_ctrl_rfu2;

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	u32 emc_pmacro_data_brick_ctrl_fdpd;

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	u32 emc_pmacro_bg_bias_ctrl_0;

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	u32 emc_cfg_3;

209
	u32 emc_pmacro_tx_pwrd_0;

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	u32 emc_pmacro_tx_pwrd_1;

211
	u32 emc_pmacro_tx_pwrd_2;

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	u32 emc_pmacro_tx_pwrd_3;

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	u32 emc_pmacro_tx_pwrd_4;

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	u32 emc_pmacro_tx_pwrd_5;

215
	u32 emc_config_sample_delay;

216
	u32 emc_pmacro_tx_sel_clk_src_0;

217
	u32 emc_pmacro_tx_sel_clk_src_1;

218
	u32 emc_pmacro_tx_sel_clk_src_2;

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	u32 emc_pmacro_tx_sel_clk_src_3;

220
	u32 emc_pmacro_tx_sel_clk_src_4;

221
	u32 emc_pmacro_tx_sel_clk_src_5;

222
	u32 emc_pmacro_ddll_bypass;

223
	u32 emc_pmacro_ddll_pwrd_0;

224
	u32 emc_pmacro_ddll_pwrd_1;

225
	u32 emc_pmacro_ddll_pwrd_2;

226
	u32 emc_pmacro_cmd_ctrl_0;

227
	u32 emc_pmacro_cmd_ctrl_1;

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	u32 emc_pmacro_cmd_ctrl_2;

229
	u32 emc_tr_timing_0;

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	u32 emc_tr_dvfs;

231
	u32 emc_tr_ctrl_1;

232
	u32 emc_tr_rdv;

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	u32 emc_tr_qpop;

234
	u32 emc_tr_rdv_mask;

235
	u32 emc_mrw14;

236
	u32 emc_tr_qsafe;

237
	u32 emc_tr_qrst;

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	u32 emc_training_ctrl;

239
	u32 emc_training_settle;

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	u32 emc_training_vref_settle;

241
	u32 emc_training_ca_fine_ctrl;

242
	u32 emc_training_ca_ctrl_misc;

243
	u32 emc_training_ca_ctrl_misc1;

244
	u32 emc_training_ca_vref_ctrl;

245
	u32 emc_training_quse_cors_ctrl;

246
	u32 emc_training_quse_fine_ctrl;

247
	u32 emc_training_quse_ctrl_misc;

248
	u32 emc_training_quse_vref_ctrl;

249
	u32 emc_training_read_fine_ctrl;

250
	u32 emc_training_read_ctrl_misc;

251
	u32 emc_training_read_vref_ctrl;

252
	u32 emc_training_write_fine_ctrl;

253
	u32 emc_training_write_ctrl_misc;

254
	u32 emc_training_write_vref_ctrl;

255
	u32 emc_training_mpc;

256
	u32 emc_mrw15;

257
} burst_regs_t;

258


259
typedef struct

260
{

261
	u32 burst_regs[221];

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	u32 burst_reg_per_ch[8];

263
	u32 shadow_regs_ca_train[221];

264
	u32 shadow_regs_quse_train[221];

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	u32 shadow_regs_rdwr_train[221];

266
} burst_regs_table_t;

267


268
typedef struct

269
{

270
	u32 ptfv_dqsosc_movavg_c0d0u0;

271
	u32 ptfv_dqsosc_movavg_c0d0u1;

272
	u32 ptfv_dqsosc_movavg_c0d1u0;

273
	u32 ptfv_dqsosc_movavg_c0d1u1;

274
	u32 ptfv_dqsosc_movavg_c1d0u0;

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	u32 ptfv_dqsosc_movavg_c1d0u1;

276
	u32 ptfv_dqsosc_movavg_c1d1u0;

277
	u32 ptfv_dqsosc_movavg_c1d1u1;

278
	u32 ptfv_write_samples;

279
	u32 ptfv_dvfs_samples;

280
	u32 ptfv_movavg_weight;

281
	u32 ptfv_config_ctrl;

282
} ptfv_list_table_t;

283


284
typedef struct

285
{

286
	u32 emc0_mrw10;

287
	u32 emc1_mrw10;

288
	u32 emc0_mrw11;

289
	u32 emc1_mrw11;

290
	u32 emc0_mrw12;

291
	u32 emc1_mrw12;

292
	u32 emc0_mrw13;

293
	u32 emc1_mrw13;

294
} burst_reg_per_ch_t;

295


296
typedef struct

297
{

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	u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;

299
	u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;

300
	u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;

301
	u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;

302
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;

303
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;

304
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;

305
	u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;

306
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;

307
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;

308
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;

309
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;

310
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;

311
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;

312
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;

313
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;

314
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;

315
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;

316
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;

317
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;

318
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;

319
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;

320
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;

321
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;

322
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;

323
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;

324
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;

325
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;

326
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;

327
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;

328
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;

329
	u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;

330
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;

331
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;

332
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;

333
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;

334
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;

335
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;

336
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;

337
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;

338
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;

339
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;

340
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;

341
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;

342
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;

343
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;

344
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;

345
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;

346
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;

347
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;

348
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;

349
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;

350
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;

351
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;

352
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;

353
	u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;

354
	u32 emc_pmacro_ib_vref_dqs_0;

355
	u32 emc_pmacro_ib_vref_dqs_1;

356
	u32 emc_pmacro_ib_vref_dq_0;

357
	u32 emc_pmacro_ib_vref_dq_1;

358
	u32 emc_pmacro_ob_ddll_long_dq_rank0_0;

359
	u32 emc_pmacro_ob_ddll_long_dq_rank0_1;

360
	u32 emc_pmacro_ob_ddll_long_dq_rank0_2;

361
	u32 emc_pmacro_ob_ddll_long_dq_rank0_3;

362
	u32 emc_pmacro_ob_ddll_long_dq_rank0_4;

363
	u32 emc_pmacro_ob_ddll_long_dq_rank0_5;

364
	u32 emc_pmacro_ob_ddll_long_dq_rank1_0;

365
	u32 emc_pmacro_ob_ddll_long_dq_rank1_1;

366
	u32 emc_pmacro_ob_ddll_long_dq_rank1_2;

367
	u32 emc_pmacro_ob_ddll_long_dq_rank1_3;

368
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;

369
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;

370
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;

371
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;

372
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;

373
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;

374
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;

375
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;

376
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;

377
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;

378
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;

379
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;

380
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;

381
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;

382
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;

383
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;

384
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;

385
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;

386
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;

387
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;

388
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;

389
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;

390
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;

391
	u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;

392
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;

393
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;

394
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;

395
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;

396
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;

397
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;

398
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;

399
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;

400
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;

401
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;

402
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;

403
	u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;

404
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;

405
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;

406
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;

407
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;

408
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;

409
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;

410
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;

411
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;

412
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;

413
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;

414
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;

415
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;

416
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;

417
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;

418
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;

419
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;

420
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;

421
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;

422
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;

423
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;

424
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;

425
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;

426
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;

427
	u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;

428
	u32 emc_pmacro_quse_ddll_rank0_0;

429
	u32 emc_pmacro_quse_ddll_rank0_1;

430
	u32 emc_pmacro_quse_ddll_rank0_2;

431
	u32 emc_pmacro_quse_ddll_rank0_3;

432
	u32 emc_pmacro_quse_ddll_rank1_0;

433
	u32 emc_pmacro_quse_ddll_rank1_1;

434
	u32 emc_pmacro_quse_ddll_rank1_2;

435
	u32 emc_pmacro_quse_ddll_rank1_3;

436
} trim_regs_t;

437


438
typedef struct

439
{

440
	u32 emc_cmd_brlshft_0;

441
	u32 emc_cmd_brlshft_1;

442
	u32 emc0_data_brlshft_0;

443
	u32 emc1_data_brlshft_0;

444
	u32 emc0_data_brlshft_1;

445
	u32 emc1_data_brlshft_1;

446
	u32 emc_quse_brlshft_0;

447
	u32 emc_quse_brlshft_1;

448
	u32 emc_quse_brlshft_2;

449
	u32 emc_quse_brlshft_3;

450
} trim_perch_regs_t;

451


452
typedef struct

453
{

454
	u32 t_rp;

455
	u32 t_fc_lpddr4;

456
	u32 t_rfc;

457
	u32 t_pdex;

458
	u32 rl;

459
} dram_timings_t;

460


461
typedef struct

462
{

463
	u32 emc0_training_opt_dqs_ib_vref_rank0;

464
	u32 emc1_training_opt_dqs_ib_vref_rank0;

465
	u32 emc0_training_opt_dqs_ib_vref_rank1;

466
	u32 emc1_training_opt_dqs_ib_vref_rank1;

467
} vref_perch_regs_t;

468


469
typedef struct

470
{

471
	u32 trim_regs[138];

472
	u32 trim_perch_regs[10];

473
	u32 vref_perch_regs[4];

474
} trim_regs_table_t;

475


476
typedef struct

477
{

478
	u32 rev;

479
	char dvfs_ver[60];

480
	u32 rate_khz;

481
	u32 min_volt;

482
	u32 gpu_min_volt;

483
	char clock_src[32];

484
	u32 clk_src_emc;

485
	u32 needs_training;

486
	u32 training_pattern;

487
	u32 trained;

488
	u32 periodic_training;

489
	u32 trained_dram_clktree_c0d0u0;

490
	u32 trained_dram_clktree_c0d0u1;

491
	u32 trained_dram_clktree_c0d1u0;

492
	u32 trained_dram_clktree_c0d1u1;

493
	u32 trained_dram_clktree_c1d0u0;

494
	u32 trained_dram_clktree_c1d0u1;

495
	u32 trained_dram_clktree_c1d1u0;

496
	u32 trained_dram_clktree_c1d1u1;

497
	u32 current_dram_clktree_c0d0u0;

498
	u32 current_dram_clktree_c0d0u1;

499
	u32 current_dram_clktree_c0d1u0;

500
	u32 current_dram_clktree_c0d1u1;

501
	u32 current_dram_clktree_c1d0u0;

502
	u32 current_dram_clktree_c1d0u1;

503
	u32 current_dram_clktree_c1d1u0;

504
	u32 current_dram_clktree_c1d1u1;

505
	u32 run_clocks;

506
	u32 tree_margin;

507
	u32 num_burst;

508
	u32 num_burst_per_ch;

509
	u32 num_trim;

510
	u32 num_trim_per_ch;

511
	u32 num_mc_regs;

512
	u32 num_up_down;

513
	u32 vref_num;

514
	u32 training_mod_num;

515
	u32 dram_timing_num;

516


517
	ptfv_list_table_t ptfv_list;

518


519
	burst_regs_t burst_regs;

520
	burst_reg_per_ch_t burst_reg_per_ch;

521
	burst_regs_t shadow_regs_ca_train;

522
	burst_regs_t shadow_regs_quse_train;

523
	burst_regs_t shadow_regs_rdwr_train;

524
	trim_regs_t trim_regs;

525
	trim_perch_regs_t trim_perch_regs;

526
	vref_perch_regs_t vref_perch_regs;

527
	dram_timings_t dram_timings;

528


529
	u32 training_mod_regs[20];

530
	u32 save_restore_mod_regs[12];

531
	u32 burst_mc_regs[33];

532
	u32 la_scale_regs[24];

533


534
	u32 min_mrs_wait;

535
	u32 emc_mrw;

536
	u32 emc_mrw2;

537
	u32 emc_mrw3;

538
	u32 emc_mrw4;

539
	u32 emc_mrw9;

540
	u32 emc_mrs;

541
	u32 emc_emrs;

542
	u32 emc_emrs2;

543
	u32 emc_auto_cal_config;

544
	u32 emc_auto_cal_config2;

545
	u32 emc_auto_cal_config3;

546
	u32 emc_auto_cal_config4;

547
	u32 emc_auto_cal_config5;

548
	u32 emc_auto_cal_config6;

549
	u32 emc_auto_cal_config7;

550
	u32 emc_auto_cal_config8;

551
	u32 emc_cfg_2;

552
	u32 emc_sel_dpd_ctrl;

553
	u32 emc_fdpd_ctrl_cmd_no_ramp;

554
	u32 dll_clk_src;

555
	u32 clk_out_enb_x_0_clk_enb_emc_dll;

556
	u32 latency;

557
} emc_table_t;

558


559
#endif

560