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// SPDX-FileCopyrightText: 2019-2025 Connor McLaughlin <[email protected]>
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// SPDX-License-Identifier: CC-BY-NC-ND-4.0
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#pragma once
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#include "cpu_types.h"
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#include "gte_types.h"
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#include "types.h"
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#include "common/bitfield.h"
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#include <array>
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#include <optional>
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#include <string>
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#include <vector>
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class StateWrapper;
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class SmallStringBase;
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namespace CPU {
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enum : VirtualMemoryAddress
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{
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  RESET_VECTOR = UINT32_C(0xBFC00000)
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};
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enum : PhysicalMemoryAddress
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{
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  SCRATCHPAD_ADDR = UINT32_C(0x1F800000),
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  SCRATCHPAD_ADDR_MASK = UINT32_C(0x7FFFFC00),
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  SCRATCHPAD_OFFSET_MASK = UINT32_C(0x000003FF),
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  SCRATCHPAD_SIZE = UINT32_C(0x00000400),
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  ICACHE_SIZE = UINT32_C(0x00001000),
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  ICACHE_SLOTS = ICACHE_SIZE / sizeof(u32),
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  ICACHE_LINE_SIZE = 16,
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  ICACHE_LINES = ICACHE_SIZE / ICACHE_LINE_SIZE,
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  ICACHE_WORDS_PER_LINE = ICACHE_SLOTS / ICACHE_LINES,
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  ICACHE_TAG_ADDRESS_MASK = 0xFFFFFFF0u,
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  ICACHE_INVALID_BITS = 0x0Fu,
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};
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union CacheControl
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{
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  u32 bits;
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  BitField<u32, bool, 0, 1> lock_mode;
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  BitField<u32, bool, 1, 1> invalidate_mode;
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  BitField<u32, bool, 2, 1> tag_test_mode;
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  BitField<u32, bool, 3, 1> dcache_scratchpad;
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  BitField<u32, bool, 7, 1> dcache_enable;
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  BitField<u32, u8, 8, 2> icache_fill_size; // actually dcache? icache always fills to 16 bytes
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  BitField<u32, bool, 11, 1> icache_enable;
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};
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struct PGXPValue
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{
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  float x;
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  float y;
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  float z;
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  u32 value;
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  u32 flags;
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  ALWAYS_INLINE void Validate(u32 psxval) { flags = (value == psxval) ? flags : 0; }
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  ALWAYS_INLINE float GetValidX(u32 psxval) const
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  {
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    return (flags & 1) ? x : static_cast<float>(static_cast<s16>(psxval));
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  }
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  ALWAYS_INLINE float GetValidY(u32 psxval) const
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  {
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    return (flags & 2) ? y : static_cast<float>(static_cast<s16>(psxval >> 16));
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  }
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};
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struct ALIGN_TO_CACHE_LINE State
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{
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  // ticks the CPU has executed
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  u32 downcount = 0;
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  u32 pending_ticks = 0;
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  u32 gte_completion_tick = 0;
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  u32 muldiv_completion_tick = 0;
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  Registers regs = {};
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  Cop0Registers cop0_regs = {};
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  u32 pc = 0;  // at execution time: the address of the next instruction to execute (already fetched)
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  u32 npc = 0; // at execution time: the address of the next instruction to fetch
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  // address of the instruction currently being executed
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  Instruction current_instruction = {};
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  u32 current_instruction_pc = 0;
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  bool current_instruction_in_branch_delay_slot = false;
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  bool current_instruction_was_branch_taken = false;
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  bool next_instruction_is_branch_delay_slot = false;
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  bool branch_was_taken = false;
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  bool exception_raised = false;
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  bool bus_error = false;
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  // load delays
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  Reg load_delay_reg = Reg::count;
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  Reg next_load_delay_reg = Reg::count;
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  u32 load_delay_value = 0;
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  u32 next_load_delay_value = 0;
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  Instruction next_instruction = {};
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  CacheControl cache_control{0};
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  // GTE registers are stored here so we can access them on ARM with a single instruction
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  GTE::Regs gte_regs = {};
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  // 2 bytes of padding here on x64
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  bool using_interpreter = false;
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  bool using_debug_dispatcher = false;
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  void* fastmem_base = nullptr;
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  void** memory_handlers = nullptr;
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  PGXPValue pgxp_gpr[static_cast<u8>(Reg::count)] = {};
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  PGXPValue pgxp_cop0[32] = {};
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  PGXPValue pgxp_gte[64] = {};
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  std::array<u32, ICACHE_LINES> icache_tags = {};
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  std::array<u32, ICACHE_LINES * ICACHE_WORDS_PER_LINE> icache_data = {};
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  std::array<u8, SCRATCHPAD_SIZE> scratchpad = {};
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  static constexpr u32 GPRRegisterOffset(u32 index) { return OFFSETOF(State, regs.r) + (sizeof(u32) * index); }
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  static constexpr u32 GTERegisterOffset(u32 index) { return OFFSETOF(State, gte_regs.r32) + (sizeof(u32) * index); }
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};
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extern State g_state;
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void Initialize();
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void Shutdown();
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void Reset();
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bool DoState(StateWrapper& sw);
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void ClearICache();
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CPUExecutionMode GetCurrentExecutionMode();
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bool UpdateDebugDispatcherFlag();
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void UpdateMemoryPointers();
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/// Executes interpreter loop.
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void Execute();
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// Forces an early exit from the CPU dispatcher.
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[[noreturn]] void ExitExecution();
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ALWAYS_INLINE Registers& GetRegs()
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{
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  return g_state.regs;
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}
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ALWAYS_INLINE u32 GetPendingTicks()
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{
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  return g_state.pending_ticks;
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}
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ALWAYS_INLINE void ResetPendingTicks()
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{
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  g_state.gte_completion_tick =
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    (g_state.pending_ticks < g_state.gte_completion_tick) ? (g_state.gte_completion_tick - g_state.pending_ticks) : 0;
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  g_state.muldiv_completion_tick = (g_state.pending_ticks < g_state.muldiv_completion_tick) ?
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                                     (g_state.muldiv_completion_tick - g_state.pending_ticks) :
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                                     0;
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  g_state.pending_ticks = 0;
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}
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ALWAYS_INLINE void AddPendingTicks(TickCount ticks)
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{
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  g_state.pending_ticks += static_cast<u32>(ticks);
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}
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// state helpers
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ALWAYS_INLINE bool InUserMode()
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{
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  return g_state.cop0_regs.sr.KUc;
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}
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ALWAYS_INLINE bool InKernelMode()
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{
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  return !g_state.cop0_regs.sr.KUc;
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}
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// Memory reads variants which do not raise exceptions.
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// These methods do not support writing to MMIO addresses with side effects, and are
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// thus safe to call from the UI thread in debuggers, for example.
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bool SafeReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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bool SafeReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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bool SafeReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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bool SafeReadMemoryCString(VirtualMemoryAddress addr, SmallStringBase* value, u32 max_length = 1024);
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bool SafeReadMemoryBytes(VirtualMemoryAddress addr, void* data, u32 length);
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bool SafeWriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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bool SafeWriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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bool SafeWriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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bool SafeWriteMemoryBytes(VirtualMemoryAddress addr, const void* data, u32 length);
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bool SafeWriteMemoryBytes(VirtualMemoryAddress addr, const std::span<const u8> data);
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bool SafeZeroMemoryBytes(VirtualMemoryAddress addr, u32 length);
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// External IRQs
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void SetIRQRequest(bool state);
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void DisassembleAndPrint(u32 addr);
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void DisassembleAndLog(u32 addr);
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void DisassembleAndPrint(u32 addr, u32 instructions_before, u32 instructions_after);
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// Write to CPU execution log file.
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void WriteToExecutionLog(const char* format, ...) PRINTFLIKE(1, 2);
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// Trace Routines
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bool IsTraceEnabled();
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void StartTrace();
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void StopTrace();
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// Breakpoint types - execute => breakpoint, read/write => watchpoints
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enum class BreakpointType : u8
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{
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  Execute,
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  Read,
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  Write,
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  Count
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};
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// Breakpoint callback - if the callback returns false, the breakpoint will be removed.
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using BreakpointCallback = bool (*)(BreakpointType type, VirtualMemoryAddress pc, VirtualMemoryAddress memaddr);
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struct Breakpoint
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{
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  VirtualMemoryAddress address;
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  BreakpointCallback callback;
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  u32 number;
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  u32 hit_count;
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  BreakpointType type;
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  bool auto_clear;
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  bool enabled;
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};
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using BreakpointList = std::vector<Breakpoint>;
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// Breakpoints
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const char* GetBreakpointTypeName(BreakpointType type);
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bool HasAnyBreakpoints();
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bool HasBreakpointAtAddress(BreakpointType type, VirtualMemoryAddress address);
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BreakpointList CopyBreakpointList(bool include_auto_clear = false, bool include_callbacks = false);
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bool AddBreakpoint(BreakpointType type, VirtualMemoryAddress address, bool auto_clear = false, bool enabled = true);
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bool AddBreakpointWithCallback(BreakpointType type, VirtualMemoryAddress address, BreakpointCallback callback);
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bool SetBreakpointEnabled(BreakpointType type, VirtualMemoryAddress address, bool enabled);
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bool RemoveBreakpoint(BreakpointType type, VirtualMemoryAddress address);
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void ClearBreakpoints();
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bool AddStepOverBreakpoint();
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bool AddStepOutBreakpoint(u32 max_instructions_to_search = 1000);
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void SetSingleStepFlag();
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extern bool TRACE_EXECUTION;
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// Debug register introspection
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struct DebuggerRegisterListEntry
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{
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  const char* name;
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  u32* value_ptr;
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};
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inline constexpr u32 NUM_DEBUGGER_REGISTER_LIST_ENTRIES = 103;
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extern const std::array<DebuggerRegisterListEntry, NUM_DEBUGGER_REGISTER_LIST_ENTRIES> g_debugger_register_list;
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} // namespace CPU
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