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// SPDX-FileCopyrightText: 2016 iCatButler, 2019-2024 Connor McLaughlin <[email protected]>
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// SPDX-License-Identifier: CC-BY-NC-ND-4.0
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#pragma once
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#include "cpu_core.h"
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namespace CPU::PGXP {
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/// State management.
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void Initialize();
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void Reset();
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void Shutdown();
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/// Returns memory usage to serialize additional PGXP state.
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size_t GetStateSize();
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/// Save/load additional PGXP state.
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void DoState(StateWrapper& sw);
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/// Vertex lookup from GPU side.
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bool GetPreciseVertex(u32 addr, u32 value, int x, int y, int xOffs, int yOffs, float* out_x, float* out_y,
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                      float* out_w);
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// GTE instruction hooks.
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void GTE_RTPS(float x, float y, float z, u32 value);
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bool GTE_HasPreciseVertices(u32 sxy0, u32 sxy1, u32 sxy2);
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float GTE_NCLIP();
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// CPU instruction implementations.
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void CPU_MFC2(Instruction instr, u32 rdVal);
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void CPU_MTC2(Instruction instr, u32 rtVal);
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void CPU_LWC2(Instruction instr, u32 addr, u32 rtVal);
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void CPU_SWC2(Instruction instr, u32 addr, u32 rtVal);
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void CPU_LW(Instruction instr, u32 addr, u32 rtVal);
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void CPU_LH(Instruction instr, u32 addr, u32 rtVal);
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void CPU_LHU(Instruction instr, u32 addr, u32 rtVal);
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void CPU_LBx(Instruction instr, u32 addr, u32 rtVal);
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void CPU_LWx(Instruction instr, u32 addr, u32 rtVal);
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void CPU_SB(Instruction instr, u32 addr, u32 rtVal);
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void CPU_SH(Instruction instr, u32 addr, u32 rtVal);
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void CPU_SW(Instruction instr, u32 addr, u32 rtVal);
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void CPU_SWx(Instruction instr, u32 addr, u32 rtVal);
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void CPU_MOVE(u32 Rd, u32 Rs, u32 rsVal);
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void CPU_MOVE_Packed(u32 rd_and_rs, u32 rsVal);
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void CPU_ADDI(Instruction instr, u32 rsVal);
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void CPU_ANDI(Instruction instr, u32 rsVal);
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void CPU_ORI(Instruction instr, u32 rsVal);
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void CPU_XORI(Instruction instr, u32 rsVal);
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void CPU_SLTI(Instruction instr, u32 rsVal);
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void CPU_SLTIU(Instruction instr, u32 rsVal);
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void CPU_LUI(Instruction instr);
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void CPU_ADD(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_SUB(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_AND_(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_OR_(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_XOR_(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_NOR(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_SLT(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_SLTU(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_MULT(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_MULTU(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_DIV(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_DIVU(Instruction instr, u32 rsVal, u32 rtVal);
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void CPU_SLL(Instruction instr, u32 rtVal);
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void CPU_SRL(Instruction instr, u32 rtVal);
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void CPU_SRA(Instruction instr, u32 rtVal);
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void CPU_SLLV(Instruction instr, u32 rtVal, u32 rsVal);
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void CPU_SRLV(Instruction instr, u32 rtVal, u32 rsVal);
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void CPU_SRAV(Instruction instr, u32 rtVal, u32 rsVal);
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void CPU_MFC0(Instruction instr, u32 rdVal);
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void CPU_MTC0(Instruction instr, u32 rdVal, u32 rtVal);
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// Utility functions.
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ALWAYS_INLINE u32 PackMoveArgs(Reg rd, Reg rs)
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{
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  return (static_cast<u32>(rd) << 8) | static_cast<u32>(rs);
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}
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ALWAYS_INLINE void TryMove(Reg rd, Reg rs, Reg rt)
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{
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  u32 src;
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  if (rs == Reg::zero)
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    src = static_cast<u32>(rt);
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  else if (rt == Reg::zero)
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    src = static_cast<u32>(rs);
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  else
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    return;
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  CPU_MOVE(static_cast<u32>(rd), src, g_state.regs.r[src]);
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}
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ALWAYS_INLINE void TryMoveImm(Reg rd, Reg rs, u32 imm)
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{
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  if (imm == 0)
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  {
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    const u32 src = static_cast<u32>(rs);
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    CPU_MOVE(static_cast<u32>(rd), src, g_state.regs.r[src]);
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  }
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}
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} // namespace CPU::PGXP
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