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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ASM_KVM_CACHE_REGS_H
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#define ASM_KVM_CACHE_REGS_H
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#include <linux/kvm_host.h>
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#define KVM_POSSIBLE_CR0_GUEST_BITS	(X86_CR0_TS | X86_CR0_WP)
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#define KVM_POSSIBLE_CR4_GUEST_BITS				  \
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	(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR  \
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	 | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE \
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	 | X86_CR4_CET)
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#define X86_CR0_PDPTR_BITS    (X86_CR0_CD | X86_CR0_NW | X86_CR0_PG)
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#define X86_CR4_TLBFLUSH_BITS (X86_CR4_PGE | X86_CR4_PCIDE | X86_CR4_PAE | X86_CR4_SMEP)
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#define X86_CR4_PDPTR_BITS    (X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_SMEP)
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static_assert(!(KVM_POSSIBLE_CR0_GUEST_BITS & X86_CR0_PDPTR_BITS));
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#define BUILD_KVM_GPR_ACCESSORS(lname, uname)				      \
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static __always_inline unsigned long kvm_##lname##_read(struct kvm_vcpu *vcpu)\
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{									      \
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	return vcpu->arch.regs[VCPU_REGS_##uname];			      \
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}									      \
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static __always_inline void kvm_##lname##_write(struct kvm_vcpu *vcpu,	      \
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						unsigned long val)	      \
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{									      \
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	vcpu->arch.regs[VCPU_REGS_##uname] = val;			      \
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}
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BUILD_KVM_GPR_ACCESSORS(rax, RAX)
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BUILD_KVM_GPR_ACCESSORS(rbx, RBX)
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BUILD_KVM_GPR_ACCESSORS(rcx, RCX)
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BUILD_KVM_GPR_ACCESSORS(rdx, RDX)
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BUILD_KVM_GPR_ACCESSORS(rbp, RBP)
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BUILD_KVM_GPR_ACCESSORS(rsi, RSI)
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BUILD_KVM_GPR_ACCESSORS(rdi, RDI)
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#ifdef CONFIG_X86_64
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BUILD_KVM_GPR_ACCESSORS(r8,  R8)
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BUILD_KVM_GPR_ACCESSORS(r9,  R9)
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BUILD_KVM_GPR_ACCESSORS(r10, R10)
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BUILD_KVM_GPR_ACCESSORS(r11, R11)
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BUILD_KVM_GPR_ACCESSORS(r12, R12)
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BUILD_KVM_GPR_ACCESSORS(r13, R13)
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BUILD_KVM_GPR_ACCESSORS(r14, R14)
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BUILD_KVM_GPR_ACCESSORS(r15, R15)
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#endif
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/*
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 * Using the register cache from interrupt context is generally not allowed, as
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 * caching a register and marking it available/dirty can't be done atomically,
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 * i.e. accesses from interrupt context may clobber state or read stale data if
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 * the vCPU task is in the process of updating the cache.  The exception is if
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 * KVM is handling a PMI IRQ/NMI VM-Exit, as that bound code sequence doesn't
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 * touch the cache, it runs after the cache is reset (post VM-Exit), and PMIs
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 * need to access several registers that are cacheable.
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 */
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#define kvm_assert_register_caching_allowed(vcpu)		\
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	lockdep_assert_once(in_task() || kvm_arch_pmi_in_guest(vcpu))
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/*
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 * avail  dirty
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 * 0	  0	  register in VMCS/VMCB
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 * 0	  1	  *INVALID*
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 * 1	  0	  register in vcpu->arch
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 * 1	  1	  register in vcpu->arch, needs to be stored back
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 */
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static inline bool kvm_register_is_available(struct kvm_vcpu *vcpu,
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					     enum kvm_reg reg)
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{
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	kvm_assert_register_caching_allowed(vcpu);
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	return test_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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}
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static inline bool kvm_register_is_dirty(struct kvm_vcpu *vcpu,
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					 enum kvm_reg reg)
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{
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	kvm_assert_register_caching_allowed(vcpu);
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	return test_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty);
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}
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static inline void kvm_register_mark_available(struct kvm_vcpu *vcpu,
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					       enum kvm_reg reg)
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{
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	kvm_assert_register_caching_allowed(vcpu);
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	__set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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}
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static inline void kvm_register_mark_dirty(struct kvm_vcpu *vcpu,
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					   enum kvm_reg reg)
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{
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	kvm_assert_register_caching_allowed(vcpu);
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	__set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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	__set_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty);
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}
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/*
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 * kvm_register_test_and_mark_available() is a special snowflake that uses an
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 * arch bitop directly to avoid the explicit instrumentation that comes with
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 * the generic bitops.  This allows code that cannot be instrumented (noinstr
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 * functions), e.g. the low level VM-Enter/VM-Exit paths, to cache registers.
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 */
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static __always_inline bool kvm_register_test_and_mark_available(struct kvm_vcpu *vcpu,
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								 enum kvm_reg reg)
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{
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	kvm_assert_register_caching_allowed(vcpu);
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	return arch___test_and_set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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}
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/*
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 * The "raw" register helpers are only for cases where the full 64 bits of a
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 * register are read/written irrespective of current vCPU mode.  In other words,
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 * odds are good you shouldn't be using the raw variants.
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 */
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static inline unsigned long kvm_register_read_raw(struct kvm_vcpu *vcpu, int reg)
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{
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	if (WARN_ON_ONCE((unsigned int)reg >= NR_VCPU_REGS))
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		return 0;
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	if (!kvm_register_is_available(vcpu, reg))
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		kvm_x86_call(cache_reg)(vcpu, reg);
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	return vcpu->arch.regs[reg];
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}
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static inline void kvm_register_write_raw(struct kvm_vcpu *vcpu, int reg,
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					  unsigned long val)
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{
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	if (WARN_ON_ONCE((unsigned int)reg >= NR_VCPU_REGS))
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		return;
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	vcpu->arch.regs[reg] = val;
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	kvm_register_mark_dirty(vcpu, reg);
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}
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static inline unsigned long kvm_rip_read(struct kvm_vcpu *vcpu)
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{
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	return kvm_register_read_raw(vcpu, VCPU_REGS_RIP);
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}
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static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val)
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{
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	kvm_register_write_raw(vcpu, VCPU_REGS_RIP, val);
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}
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static inline unsigned long kvm_rsp_read(struct kvm_vcpu *vcpu)
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{
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	return kvm_register_read_raw(vcpu, VCPU_REGS_RSP);
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}
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static inline void kvm_rsp_write(struct kvm_vcpu *vcpu, unsigned long val)
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{
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	kvm_register_write_raw(vcpu, VCPU_REGS_RSP, val);
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}
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static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index)
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{
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	might_sleep();  /* on svm */
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	if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
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		kvm_x86_call(cache_reg)(vcpu, VCPU_EXREG_PDPTR);
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	return vcpu->arch.walk_mmu->pdptrs[index];
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}
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static inline void kvm_pdptr_write(struct kvm_vcpu *vcpu, int index, u64 value)
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{
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	vcpu->arch.walk_mmu->pdptrs[index] = value;
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}
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static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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	ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS;
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	if ((tmask & vcpu->arch.cr0_guest_owned_bits) &&
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	    !kvm_register_is_available(vcpu, VCPU_EXREG_CR0))
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		kvm_x86_call(cache_reg)(vcpu, VCPU_EXREG_CR0);
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	return vcpu->arch.cr0 & mask;
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}
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static __always_inline bool kvm_is_cr0_bit_set(struct kvm_vcpu *vcpu,
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					       unsigned long cr0_bit)
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{
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	BUILD_BUG_ON(!is_power_of_2(cr0_bit));
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	return !!kvm_read_cr0_bits(vcpu, cr0_bit);
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}
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static inline ulong kvm_read_cr0(struct kvm_vcpu *vcpu)
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{
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	return kvm_read_cr0_bits(vcpu, ~0UL);
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}
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static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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	ulong tmask = mask & KVM_POSSIBLE_CR4_GUEST_BITS;
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	if ((tmask & vcpu->arch.cr4_guest_owned_bits) &&
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	    !kvm_register_is_available(vcpu, VCPU_EXREG_CR4))
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		kvm_x86_call(cache_reg)(vcpu, VCPU_EXREG_CR4);
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	return vcpu->arch.cr4 & mask;
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}
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static __always_inline bool kvm_is_cr4_bit_set(struct kvm_vcpu *vcpu,
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					       unsigned long cr4_bit)
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{
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	BUILD_BUG_ON(!is_power_of_2(cr4_bit));
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	return !!kvm_read_cr4_bits(vcpu, cr4_bit);
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}
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static inline ulong kvm_read_cr3(struct kvm_vcpu *vcpu)
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{
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	if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
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		kvm_x86_call(cache_reg)(vcpu, VCPU_EXREG_CR3);
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	return vcpu->arch.cr3;
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}
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static inline ulong kvm_read_cr4(struct kvm_vcpu *vcpu)
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{
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	return kvm_read_cr4_bits(vcpu, ~0UL);
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}
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static inline u64 kvm_read_edx_eax(struct kvm_vcpu *vcpu)
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{
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	return (kvm_rax_read(vcpu) & -1u)
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		| ((u64)(kvm_rdx_read(vcpu) & -1u) << 32);
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}
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static inline void enter_guest_mode(struct kvm_vcpu *vcpu)
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{
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	vcpu->arch.hflags |= HF_GUEST_MASK;
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	vcpu->stat.guest_mode = 1;
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}
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static inline void leave_guest_mode(struct kvm_vcpu *vcpu)
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{
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	vcpu->arch.hflags &= ~HF_GUEST_MASK;
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	if (vcpu->arch.load_eoi_exitmap_pending) {
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		vcpu->arch.load_eoi_exitmap_pending = false;
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		kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
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	}
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	vcpu->stat.guest_mode = 0;
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}
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static inline bool is_guest_mode(struct kvm_vcpu *vcpu)
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{
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	return vcpu->arch.hflags & HF_GUEST_MASK;
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}
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#endif
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