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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_LAPIC_H
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#define __KVM_X86_LAPIC_H
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#include <kvm/iodev.h>
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#include <asm/apic.h>
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#include <linux/kvm_host.h>
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#include "hyperv.h"
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#include "smm.h"
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#define KVM_APIC_INIT		0
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#define KVM_APIC_SIPI		1
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#define APIC_SHORT_MASK			0xc0000
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#define APIC_DEST_NOSHORT		0x0
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#define APIC_DEST_MASK			0x800
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#define APIC_BUS_CYCLE_NS_DEFAULT	1
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#define APIC_BROADCAST			0xFF
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#define X2APIC_BROADCAST		0xFFFFFFFFul
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#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
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enum lapic_mode {
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	LAPIC_MODE_DISABLED = 0,
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	LAPIC_MODE_INVALID = X2APIC_ENABLE,
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	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
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	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
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};
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enum lapic_lvt_entry {
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	LVT_TIMER,
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	LVT_THERMAL_MONITOR,
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	LVT_PERFORMANCE_COUNTER,
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	LVT_LINT0,
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	LVT_LINT1,
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	LVT_ERROR,
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	LVT_CMCI,
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	KVM_APIC_MAX_NR_LVT_ENTRIES,
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};
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#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
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struct kvm_timer {
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	struct hrtimer timer;
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	s64 period; 				/* unit: ns */
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	ktime_t target_expiration;
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	u32 timer_mode;
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	u32 timer_mode_mask;
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	u64 tscdeadline;
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	u64 expired_tscdeadline;
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	u32 timer_advance_ns;
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	atomic_t pending;			/* accumulated triggered timers */
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	bool hv_timer_in_use;
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};
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struct kvm_lapic {
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	unsigned long base_address;
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	struct kvm_io_device dev;
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	struct kvm_timer lapic_timer;
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	u32 divide_count;
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	struct kvm_vcpu *vcpu;
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	bool apicv_active;
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	bool sw_enabled;
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	bool irr_pending;
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	bool lvt0_in_nmi_mode;
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	/* Select registers in the vAPIC cannot be read/written. */
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	bool guest_apic_protected;
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	/* Number of bits set in ISR. */
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	s16 isr_count;
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	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
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	int highest_isr_cache;
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	/**
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	 * APIC register page.  The layout matches the register layout seen by
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	 * the guest 1:1, because it is accessed by the vmx microcode.
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	 * Note: Only one register, the TPR, is used by the microcode.
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	 */
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	void *regs;
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	gpa_t vapic_addr;
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	struct gfn_to_hva_cache vapic_cache;
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	unsigned long pending_events;
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	unsigned int sipi_vector;
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	int nr_lvt_entries;
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};
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struct dest_map;
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int kvm_create_lapic(struct kvm_vcpu *vcpu);
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void kvm_free_lapic(struct kvm_vcpu *vcpu);
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int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
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void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector);
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int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
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int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
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void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
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u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
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void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
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void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
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void kvm_apic_set_version(struct kvm_vcpu *vcpu);
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void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
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bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
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			   int shorthand, unsigned int dest, int dest_mode);
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void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
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bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr);
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bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *max_irr);
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void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
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		     struct dest_map *dest_map);
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int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
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void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
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int kvm_alloc_apic_access_page(struct kvm *kvm);
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void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);
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bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
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		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
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int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
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			     struct kvm_lapic_irq *irq,
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			     struct dest_map *dest_map);
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void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
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int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated);
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int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
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int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
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void kvm_apic_update_hwapic_isr(struct kvm_vcpu *vcpu);
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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
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u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
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void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
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void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
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void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
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int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
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void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
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void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
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int kvm_x2apic_icr_write_fast(struct kvm_lapic *apic, u64 data);
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int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
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void kvm_lapic_exit(void);
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u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
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static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
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{
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	apic_set_vector(vec, apic->regs + APIC_IRR);
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	/*
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	 * irr_pending must be true if any interrupt is pending; set it after
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	 * APIC_IRR to avoid race with apic_clear_irr
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	 */
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	apic->irr_pending = true;
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}
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static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
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{
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	return apic_get_reg(apic->regs, reg_off);
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}
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DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
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static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
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{
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	if (static_branch_unlikely(&kvm_has_noapic_vcpu))
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		return vcpu->arch.apic;
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	return true;
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}
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extern struct static_key_false_deferred apic_hw_disabled;
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static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
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{
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	if (static_branch_unlikely(&apic_hw_disabled.key))
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		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
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	return true;
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}
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extern struct static_key_false_deferred apic_sw_disabled;
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static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
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{
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	if (static_branch_unlikely(&apic_sw_disabled.key))
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		return apic->sw_enabled;
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	return true;
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}
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static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
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{
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	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
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}
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static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
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{
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	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
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}
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static inline int apic_x2apic_mode(struct kvm_lapic *apic)
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{
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	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
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}
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static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
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{
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	return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
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}
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static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
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{
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	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
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}
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static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
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{
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	return !is_smm(vcpu) &&
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	       !kvm_x86_call(apic_init_signal_blocked)(vcpu);
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}
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static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
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{
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	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
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}
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bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
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void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
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void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
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			      unsigned long *vcpu_bitmap);
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bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
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			     struct kvm_vcpu **dest_vcpu);
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void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
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void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
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void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
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bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
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void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
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static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
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{
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	return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
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}
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static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
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{
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	return kvm_apic_mode(vcpu->arch.apic_base);
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}
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static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
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{
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	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
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}
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#endif
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