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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_PMU_H
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#define __KVM_X86_PMU_H
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#include <linux/nospec.h>
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#include <asm/kvm_host.h>
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#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
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#define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
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#define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)
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#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |	\
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					  MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
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/* retrieve a fixed counter bits out of IA32_FIXED_CTR_CTRL */
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#define fixed_ctrl_field(ctrl_reg, idx) \
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	(((ctrl_reg) >> ((idx) * INTEL_FIXED_BITS_STRIDE)) & INTEL_FIXED_BITS_MASK)
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#define VMWARE_BACKDOOR_PMC_HOST_TSC		0x10000
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#define VMWARE_BACKDOOR_PMC_REAL_TIME		0x10001
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#define VMWARE_BACKDOOR_PMC_APPARENT_TIME	0x10002
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#define KVM_FIXED_PMC_BASE_IDX INTEL_PMC_IDX_FIXED
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struct kvm_pmu_ops {
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	struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
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		unsigned int idx, u64 *mask);
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	struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr);
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	int (*check_rdpmc_early)(struct kvm_vcpu *vcpu, unsigned int idx);
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	bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
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	int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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	int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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	void (*refresh)(struct kvm_vcpu *vcpu);
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	void (*init)(struct kvm_vcpu *vcpu);
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	void (*reset)(struct kvm_vcpu *vcpu);
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	void (*deliver_pmi)(struct kvm_vcpu *vcpu);
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	void (*cleanup)(struct kvm_vcpu *vcpu);
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	const u64 EVENTSEL_EVENT;
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	const int MAX_NR_GP_COUNTERS;
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	const int MIN_NR_GP_COUNTERS;
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};
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void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops);
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static inline bool kvm_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu)
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{
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	/*
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	 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is
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	 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is
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	 * greater than zero.  However, KVM only exposes and emulates the MSR
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	 * to/for the guest if the guest PMU supports at least "Architectural
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	 * Performance Monitoring Version 2".
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	 *
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	 * AMD's version of PERF_GLOBAL_CTRL conveniently shows up with v2.
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	 */
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	return pmu->version > 1;
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}
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/*
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 * KVM tracks all counters in 64-bit bitmaps, with general purpose counters
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 * mapped to bits 31:0 and fixed counters mapped to 63:32, e.g. fixed counter 0
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 * is tracked internally via index 32.  On Intel, (AMD doesn't support fixed
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 * counters), this mirrors how fixed counters are mapped to PERF_GLOBAL_CTRL
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 * and similar MSRs, i.e. tracking fixed counters at base index 32 reduces the
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 * amounter of boilerplate needed to iterate over PMCs *and* simplifies common
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 * enabling/disable/reset operations.
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 *
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 * WARNING!  This helper is only for lookups that are initiated by KVM, it is
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 * NOT safe for guest lookups, e.g. will do the wrong thing if passed a raw
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 * ECX value from RDPMC (fixed counters are accessed by setting bit 30 in ECX
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 * for RDPMC, not by adding 32 to the fixed counter index).
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 */
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static inline struct kvm_pmc *kvm_pmc_idx_to_pmc(struct kvm_pmu *pmu, int idx)
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{
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	if (idx < pmu->nr_arch_gp_counters)
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		return &pmu->gp_counters[idx];
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	idx -= KVM_FIXED_PMC_BASE_IDX;
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	if (idx >= 0 && idx < pmu->nr_arch_fixed_counters)
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		return &pmu->fixed_counters[idx];
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	return NULL;
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}
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#define kvm_for_each_pmc(pmu, pmc, i, bitmap)			\
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	for_each_set_bit(i, bitmap, X86_PMC_IDX_MAX)		\
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		if (!(pmc = kvm_pmc_idx_to_pmc(pmu, i)))	\
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			continue;				\
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		else						\
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static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
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{
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	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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	return pmu->counter_bitmask[pmc->type];
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}
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static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
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{
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	u64 counter, enabled, running;
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	counter = pmc->counter + pmc->emulated_counter;
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	if (pmc->perf_event && !pmc->is_paused)
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		counter += perf_event_read_value(pmc->perf_event,
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						 &enabled, &running);
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	/* FIXME: Scaling needed? */
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	return counter & pmc_bitmask(pmc);
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}
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void pmc_write_counter(struct kvm_pmc *pmc, u64 val);
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static inline bool pmc_is_gp(struct kvm_pmc *pmc)
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{
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	return pmc->type == KVM_PMC_GP;
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}
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static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
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{
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	return pmc->type == KVM_PMC_FIXED;
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}
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static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu,
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						 u64 data)
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{
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	return !(pmu->global_ctrl_rsvd & data);
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}
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/* returns general purpose PMC with the specified MSR. Note that it can be
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 * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a
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 * parameter to tell them apart.
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 */
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static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
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					 u32 base)
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{
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	if (msr >= base && msr < base + pmu->nr_arch_gp_counters) {
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		u32 index = array_index_nospec(msr - base,
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					       pmu->nr_arch_gp_counters);
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		return &pmu->gp_counters[index];
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	}
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	return NULL;
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}
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/* returns fixed PMC with the specified MSR */
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static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
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{
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	int base = MSR_CORE_PERF_FIXED_CTR0;
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	if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) {
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		u32 index = array_index_nospec(msr - base,
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					       pmu->nr_arch_fixed_counters);
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		return &pmu->fixed_counters[index];
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	}
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	return NULL;
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}
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static inline bool pmc_is_locally_enabled(struct kvm_pmc *pmc)
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{
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	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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	if (pmc_is_fixed(pmc))
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		return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
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					pmc->idx - KVM_FIXED_PMC_BASE_IDX) &
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					(INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER);
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	return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
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}
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extern struct x86_pmu_capability kvm_pmu_cap;
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void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops);
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void kvm_pmu_recalc_pmc_emulation(struct kvm_pmu *pmu, struct kvm_pmc *pmc);
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static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc)
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{
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	kvm_pmu_recalc_pmc_emulation(pmc_to_pmu(pmc), pmc);
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	set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
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	kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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}
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static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff)
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{
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	int bit;
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	if (!diff)
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		return;
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	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
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		set_bit(bit, pmu->reprogram_pmi);
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	kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu));
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}
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/*
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 * Check if a PMC is enabled by comparing it against global_ctrl bits.
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 *
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 * If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled.
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 */
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static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc)
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{
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	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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	if (!kvm_pmu_has_perf_global_ctrl(pmu))
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		return true;
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	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
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}
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void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
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void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
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int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
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int kvm_pmu_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx);
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bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
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int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
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void kvm_pmu_init(struct kvm_vcpu *vcpu);
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void kvm_pmu_cleanup(struct kvm_vcpu *vcpu);
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void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
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int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp);
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void kvm_pmu_instruction_retired(struct kvm_vcpu *vcpu);
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void kvm_pmu_branch_retired(struct kvm_vcpu *vcpu);
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bool is_vmware_backdoor_pmc(u32 pmc_idx);
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extern struct kvm_pmu_ops intel_pmu_ops;
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extern struct kvm_pmu_ops amd_pmu_ops;
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#endif /* __KVM_X86_PMU_H */
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