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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_H
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#define __KVM_X86_VMX_H
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#include <linux/kvm_host.h>
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#include <asm/kvm.h>
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#include <asm/intel_pt.h>
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#include <asm/perf_event.h>
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#include <asm/posted_intr.h>
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#include "capabilities.h"
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#include "../kvm_cache_regs.h"
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#include "pmu_intel.h"
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#include "vmcs.h"
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#include "vmx_ops.h"
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#include "../cpuid.h"
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#include "run_flags.h"
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#include "../mmu.h"
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#include "common.h"
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#ifdef CONFIG_X86_64
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#define MAX_NR_USER_RETURN_MSRS	7
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#else
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#define MAX_NR_USER_RETURN_MSRS	4
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#endif
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#define MAX_NR_LOADSTORE_MSRS	8
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struct vmx_msrs {
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	unsigned int		nr;
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	struct vmx_msr_entry	val[MAX_NR_LOADSTORE_MSRS];
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};
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struct vmx_uret_msr {
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	bool load_into_hardware;
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	u64 data;
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	u64 mask;
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};
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enum segment_cache_field {
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	SEG_FIELD_SEL = 0,
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	SEG_FIELD_BASE = 1,
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	SEG_FIELD_LIMIT = 2,
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	SEG_FIELD_AR = 3,
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	SEG_FIELD_NR = 4
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};
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#define RTIT_ADDR_RANGE		4
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struct pt_ctx {
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	u64 ctl;
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	u64 status;
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	u64 output_base;
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	u64 output_mask;
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	u64 cr3_match;
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	u64 addr_a[RTIT_ADDR_RANGE];
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	u64 addr_b[RTIT_ADDR_RANGE];
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};
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struct pt_desc {
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	u64 ctl_bitmask;
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	u32 num_address_ranges;
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	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
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	struct pt_ctx host;
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	struct pt_ctx guest;
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};
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/*
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 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
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 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
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 */
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struct nested_vmx {
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	/* Has the level1 guest done vmxon? */
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	bool vmxon;
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	gpa_t vmxon_ptr;
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	bool pml_full;
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	/* The guest-physical address of the current VMCS L1 keeps for L2 */
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	gpa_t current_vmptr;
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	/*
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	 * Cache of the guest's VMCS, existing outside of guest memory.
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	 * Loaded from guest memory during VMPTRLD. Flushed to guest
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	 * memory during VMCLEAR and VMPTRLD.
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	 */
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	struct vmcs12 *cached_vmcs12;
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	/*
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	 * Cache of the guest's shadow VMCS, existing outside of guest
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	 * memory. Loaded from guest memory during VM entry. Flushed
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	 * to guest memory during VM exit.
92
	 */
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	struct vmcs12 *cached_shadow_vmcs12;
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	/*
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	 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
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	 */
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	struct gfn_to_hva_cache shadow_vmcs12_cache;
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	/*
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	 * GPA to HVA cache for VMCS12
102
	 */
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	struct gfn_to_hva_cache vmcs12_cache;
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	/*
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	 * Indicates if the shadow vmcs or enlightened vmcs must be updated
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	 * with the data held by struct vmcs12.
108
	 */
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	bool need_vmcs12_to_shadow_sync;
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	bool dirty_vmcs12;
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112
	/*
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	 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
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	 * changes in MSR bitmap for L1 or switching to a different L2. Note,
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	 * this flag can only be used reliably in conjunction with a paravirt L1
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	 * which informs L0 whether any changes to MSR bitmap for L2 were done
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	 * on its side.
118
	 */
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	bool force_msr_bitmap_recalc;
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	/*
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	 * Indicates lazily loaded guest state has not yet been decached from
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	 * vmcs02.
124
	 */
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	bool need_sync_vmcs02_to_vmcs12_rare;
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	/*
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	 * vmcs02 has been initialized, i.e. state that is constant for
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	 * vmcs02 has been written to the backing VMCS.  Initialization
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	 * is delayed until L1 actually attempts to run a nested VM.
131
	 */
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	bool vmcs02_initialized;
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	bool change_vmcs01_virtual_apic_mode;
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	bool reload_vmcs01_apic_access_page;
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	bool update_vmcs01_cpu_dirty_logging;
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	bool update_vmcs01_apicv_status;
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	bool update_vmcs01_hwapic_isr;
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	/*
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	 * Enlightened VMCS has been enabled. It does not mean that L1 has to
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	 * use it. However, VMX features available to L1 will be limited based
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	 * on what the enlightened VMCS supports.
144
	 */
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	bool enlightened_vmcs_enabled;
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	/* L2 must run next, and mustn't decide to exit to L1. */
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	bool nested_run_pending;
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	/* Pending MTF VM-exit into L1.  */
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	bool mtf_pending;
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	struct loaded_vmcs vmcs02;
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	/*
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	 * Guest pages referred to in the vmcs02 with host-physical
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	 * pointers, so we must keep them pinned while L2 runs.
158
	 */
159
	struct kvm_host_map apic_access_page_map;
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	struct kvm_host_map virtual_apic_map;
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	struct kvm_host_map pi_desc_map;
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	struct pi_desc *pi_desc;
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	bool pi_pending;
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	u16 posted_intr_nv;
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	struct hrtimer preemption_timer;
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	u64 preemption_timer_deadline;
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	bool has_preemption_timer_deadline;
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	bool preemption_timer_expired;
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172
	/*
173
	 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in
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	 * order to propagate the guest's pre-VM-Enter value into vmcs02.  For
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	 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value.
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	 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_
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	 * userspace restores MSRs before nested state.  If userspace restores
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	 * MSRs after nested state, the snapshot holds garbage, but KVM can't
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	 * detect that, and the garbage value in vmcs02 will be overwritten by
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	 * MSR restoration in any case.
181
	 */
182
	u64 pre_vmenter_debugctl;
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	u64 pre_vmenter_bndcfgs;
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	u64 pre_vmenter_s_cet;
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	u64 pre_vmenter_ssp;
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	u64 pre_vmenter_ssp_tbl;
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188
	/* to migrate it to L1 if L2 writes to L1's CR8 directly */
189
	int l1_tpr_threshold;
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191
	u16 vpid02;
192
	u16 last_vpid;
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194
	struct nested_vmx_msrs msrs;
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196
	/* SMM related state */
197
	struct {
198
		/* in VMX operation on SMM entry? */
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		bool vmxon;
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		/* in guest mode on SMM entry? */
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		bool guest_mode;
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	} smm;
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#ifdef CONFIG_KVM_HYPERV
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	gpa_t hv_evmcs_vmptr;
206
	struct kvm_host_map hv_evmcs_map;
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	struct hv_enlightened_vmcs *hv_evmcs;
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#endif
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};
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struct vcpu_vmx {
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	struct kvm_vcpu       vcpu;
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	struct vcpu_vt	      vt;
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	u8                    fail;
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	u8		      x2apic_msr_bitmap_mode;
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	u32                   idt_vectoring_info;
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	ulong                 rflags;
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220
	/*
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	 * User return MSRs are always emulated when enabled in the guest, but
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	 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
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	 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
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	 * be loaded into hardware if those conditions aren't met.
225
	 */
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	struct vmx_uret_msr   guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
227
	bool                  guest_uret_msrs_loaded;
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#ifdef CONFIG_X86_64
229
	u64		      msr_guest_kernel_gs_base;
230
#endif
231

232
	u64		      spec_ctrl;
233
	u32		      msr_ia32_umwait_control;
234

235
	/*
236
	 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
237
	 * non-nested (L1) guest, it always points to vmcs01. For a nested
238
	 * guest (L2), it points to a different VMCS.
239
	 */
240
	struct loaded_vmcs    vmcs01;
241
	struct loaded_vmcs   *loaded_vmcs;
242

243
	struct msr_autoload {
244
		struct vmx_msrs guest;
245
		struct vmx_msrs host;
246
	} msr_autoload;
247

248
	struct msr_autostore {
249
		struct vmx_msrs guest;
250
	} msr_autostore;
251

252
	struct {
253
		int vm86_active;
254
		ulong save_rflags;
255
		struct kvm_segment segs[8];
256
	} rmode;
257
	struct {
258
		u32 bitmask; /* 4 bits per segment (1 bit per field) */
259
		struct kvm_save_segment {
260
			u16 selector;
261
			unsigned long base;
262
			u32 limit;
263
			u32 ar;
264
		} seg[8];
265
	} segment_cache;
266
	int vpid;
267

268
	/* Support for a guest hypervisor (nested VMX) */
269
	struct nested_vmx nested;
270

271
	/* Dynamic PLE window. */
272
	unsigned int ple_window;
273
	bool ple_window_dirty;
274

275
	/* Support for PML */
276
#define PML_LOG_NR_ENTRIES	512
277
	/* PML is written backwards: this is the first entry written by the CPU */
278
#define PML_HEAD_INDEX		(PML_LOG_NR_ENTRIES-1)
279

280
	struct page *pml_pg;
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282
	/* apic deadline value in host tsc */
283
	u64 hv_deadline_tsc;
284

285
	/*
286
	 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
287
	 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
288
	 * in msr_ia32_feature_control_valid_bits.
289
	 */
290
	u64 msr_ia32_feature_control;
291
	u64 msr_ia32_feature_control_valid_bits;
292
	/* SGX Launch Control public key hash */
293
	u64 msr_ia32_sgxlepubkeyhash[4];
294
	u64 msr_ia32_mcu_opt_ctrl;
295
	bool disable_fb_clear;
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297
	struct pt_desc pt_desc;
298
	struct lbr_desc lbr_desc;
299

300
	/* ve_info must be page aligned. */
301
	struct vmx_ve_information *ve_info;
302
};
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304
struct kvm_vmx {
305
	struct kvm kvm;
306

307
	unsigned int tss_addr;
308
	bool ept_identity_pagetable_done;
309
	gpa_t ept_identity_map_addr;
310
	/* Posted Interrupt Descriptor (PID) table for IPI virtualization */
311
	u64 *pid_table;
312
};
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314
static __always_inline struct vcpu_vt *to_vt(struct kvm_vcpu *vcpu)
315
{
316
	return &(container_of(vcpu, struct vcpu_vmx, vcpu)->vt);
317
}
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319
static __always_inline struct kvm_vcpu *vt_to_vcpu(struct vcpu_vt *vt)
320
{
321
	return &(container_of(vt, struct vcpu_vmx, vt)->vcpu);
322
}
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324
static __always_inline union vmx_exit_reason vmx_get_exit_reason(struct kvm_vcpu *vcpu)
325
{
326
	return to_vt(vcpu)->exit_reason;
327
}
328

329
static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
330
{
331
	struct vcpu_vt *vt = to_vt(vcpu);
332

333
	if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1) &&
334
	    !WARN_ON_ONCE(is_td_vcpu(vcpu)))
335
		vt->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
336

337
	return vt->exit_qualification;
338
}
339

340
static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
341
{
342
	struct vcpu_vt *vt = to_vt(vcpu);
343

344
	if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2) &&
345
	    !WARN_ON_ONCE(is_td_vcpu(vcpu)))
346
		vt->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
347

348
	return vt->exit_intr_info;
349
}
350

351
void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
352
int allocate_vpid(void);
353
void free_vpid(int vpid);
354
void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
355
void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
356
void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
357
			unsigned long fs_base, unsigned long gs_base);
358
int vmx_get_cpl(struct kvm_vcpu *vcpu);
359
int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu);
360
bool vmx_emulation_required(struct kvm_vcpu *vcpu);
361
unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
362
void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
363
u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
364
void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
365
int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
366
void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
367
void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
368
void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
369
void ept_save_pdptrs(struct kvm_vcpu *vcpu);
370
void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
371
void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
372
u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
373

374
bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
375
void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
376
bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
377
bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
378
bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
379
bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
380
void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
381
void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
382
struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
383
void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
384
void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
385
void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
386
unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
387
bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
388
		    unsigned int flags);
389
int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
390
void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
391

392
void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set);
393

394
static inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu,
395
						 u32 msr, int type)
396
{
397
	vmx_set_intercept_for_msr(vcpu, msr, type, false);
398
}
399

400
static inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu,
401
						u32 msr, int type)
402
{
403
	vmx_set_intercept_for_msr(vcpu, msr, type, true);
404
}
405

406
u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
407
u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
408

409
gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags);
410

411
void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
412

413
u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated);
414
bool vmx_is_valid_debugctl(struct kvm_vcpu *vcpu, u64 data, bool host_initiated);
415

416
#define VMX_HOST_OWNED_DEBUGCTL_BITS	(DEBUGCTLMSR_FREEZE_IN_SMM)
417

418
static inline void vmx_guest_debugctl_write(struct kvm_vcpu *vcpu, u64 val)
419
{
420
	WARN_ON_ONCE(val & VMX_HOST_OWNED_DEBUGCTL_BITS);
421

422
	val |= vcpu->arch.host_debugctl & VMX_HOST_OWNED_DEBUGCTL_BITS;
423
	vmcs_write64(GUEST_IA32_DEBUGCTL, val);
424
}
425

426
static inline u64 vmx_guest_debugctl_read(void)
427
{
428
	return vmcs_read64(GUEST_IA32_DEBUGCTL) & ~VMX_HOST_OWNED_DEBUGCTL_BITS;
429
}
430

431
static inline void vmx_reload_guest_debugctl(struct kvm_vcpu *vcpu)
432
{
433
	u64 val = vmcs_read64(GUEST_IA32_DEBUGCTL);
434

435
	if (!((val ^ vcpu->arch.host_debugctl) & VMX_HOST_OWNED_DEBUGCTL_BITS))
436
		return;
437

438
	vmx_guest_debugctl_write(vcpu, val & ~VMX_HOST_OWNED_DEBUGCTL_BITS);
439
}
440

441
/*
442
 * Note, early Intel manuals have the write-low and read-high bitmap offsets
443
 * the wrong way round.  The bitmaps control MSRs 0x00000000-0x00001fff and
444
 * 0xc0000000-0xc0001fff.  The former (low) uses bytes 0-0x3ff for reads and
445
 * 0x800-0xbff for writes.  The latter (high) uses 0x400-0x7ff for reads and
446
 * 0xc00-0xfff for writes.  MSRs not covered by either of the ranges always
447
 * VM-Exit.
448
 */
449
#define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base)      \
450
static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap,  \
451
						       u32 msr)		       \
452
{									       \
453
	int f = sizeof(unsigned long);					       \
454
									       \
455
	if (msr <= 0x1fff)						       \
456
		return bitop##_bit(msr, bitmap + base / f);		       \
457
	else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))		       \
458
		return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
459
	return (rtype)true;						       \
460
}
461
#define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop)		       \
462
	__BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read,  0x0)     \
463
	__BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
464

465
BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
466
BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
467
BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
468

469
static inline u8 vmx_get_rvi(void)
470
{
471
	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
472
}
473

474
#define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS				\
475
	(VM_ENTRY_LOAD_DEBUG_CONTROLS)
476
#ifdef CONFIG_X86_64
477
	#define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS			\
478
		(__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS |			\
479
		 VM_ENTRY_IA32E_MODE)
480
#else
481
	#define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS			\
482
		__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS
483
#endif
484
#define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS				\
485
	(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |				\
486
	 VM_ENTRY_LOAD_IA32_PAT |					\
487
	 VM_ENTRY_LOAD_IA32_EFER |					\
488
	 VM_ENTRY_LOAD_BNDCFGS |					\
489
	 VM_ENTRY_PT_CONCEAL_PIP |					\
490
	 VM_ENTRY_LOAD_IA32_RTIT_CTL |					\
491
	 VM_ENTRY_LOAD_CET_STATE)
492

493
#define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS				\
494
	(VM_EXIT_SAVE_DEBUG_CONTROLS |					\
495
	 VM_EXIT_ACK_INTR_ON_EXIT)
496
#ifdef CONFIG_X86_64
497
	#define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS			\
498
		(__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS |			\
499
		 VM_EXIT_HOST_ADDR_SPACE_SIZE)
500
#else
501
	#define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS			\
502
		__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS
503
#endif
504
#define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS				\
505
	      (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |			\
506
	       VM_EXIT_SAVE_IA32_PAT |					\
507
	       VM_EXIT_LOAD_IA32_PAT |					\
508
	       VM_EXIT_SAVE_IA32_EFER |					\
509
	       VM_EXIT_SAVE_VMX_PREEMPTION_TIMER |			\
510
	       VM_EXIT_LOAD_IA32_EFER |					\
511
	       VM_EXIT_CLEAR_BNDCFGS |					\
512
	       VM_EXIT_PT_CONCEAL_PIP |					\
513
	       VM_EXIT_CLEAR_IA32_RTIT_CTL |				\
514
	       VM_EXIT_LOAD_CET_STATE)
515

516
#define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL			\
517
	(PIN_BASED_EXT_INTR_MASK |					\
518
	 PIN_BASED_NMI_EXITING)
519
#define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL			\
520
	(PIN_BASED_VIRTUAL_NMIS |					\
521
	 PIN_BASED_POSTED_INTR |					\
522
	 PIN_BASED_VMX_PREEMPTION_TIMER)
523

524
#define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL			\
525
	(CPU_BASED_HLT_EXITING |					\
526
	 CPU_BASED_CR3_LOAD_EXITING |					\
527
	 CPU_BASED_CR3_STORE_EXITING |					\
528
	 CPU_BASED_UNCOND_IO_EXITING |					\
529
	 CPU_BASED_MOV_DR_EXITING |					\
530
	 CPU_BASED_USE_TSC_OFFSETTING |					\
531
	 CPU_BASED_MWAIT_EXITING |					\
532
	 CPU_BASED_MONITOR_EXITING |					\
533
	 CPU_BASED_INVLPG_EXITING |					\
534
	 CPU_BASED_RDPMC_EXITING |					\
535
	 CPU_BASED_INTR_WINDOW_EXITING)
536

537
#ifdef CONFIG_X86_64
538
	#define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL		\
539
		(__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL |		\
540
		 CPU_BASED_CR8_LOAD_EXITING |				\
541
		 CPU_BASED_CR8_STORE_EXITING)
542
#else
543
	#define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL		\
544
		__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL
545
#endif
546

547
#define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL			\
548
	(CPU_BASED_RDTSC_EXITING |					\
549
	 CPU_BASED_TPR_SHADOW |						\
550
	 CPU_BASED_USE_IO_BITMAPS |					\
551
	 CPU_BASED_MONITOR_TRAP_FLAG |					\
552
	 CPU_BASED_USE_MSR_BITMAPS |					\
553
	 CPU_BASED_NMI_WINDOW_EXITING |					\
554
	 CPU_BASED_PAUSE_EXITING |					\
555
	 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS |			\
556
	 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)
557

558
#define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0
559
#define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL			\
560
	(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |			\
561
	 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |			\
562
	 SECONDARY_EXEC_WBINVD_EXITING |				\
563
	 SECONDARY_EXEC_ENABLE_VPID |					\
564
	 SECONDARY_EXEC_ENABLE_EPT |					\
565
	 SECONDARY_EXEC_UNRESTRICTED_GUEST |				\
566
	 SECONDARY_EXEC_PAUSE_LOOP_EXITING |				\
567
	 SECONDARY_EXEC_DESC |						\
568
	 SECONDARY_EXEC_ENABLE_RDTSCP |					\
569
	 SECONDARY_EXEC_ENABLE_INVPCID |				\
570
	 SECONDARY_EXEC_APIC_REGISTER_VIRT |				\
571
	 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |				\
572
	 SECONDARY_EXEC_SHADOW_VMCS |					\
573
	 SECONDARY_EXEC_ENABLE_XSAVES |					\
574
	 SECONDARY_EXEC_RDSEED_EXITING |				\
575
	 SECONDARY_EXEC_RDRAND_EXITING |				\
576
	 SECONDARY_EXEC_ENABLE_PML |					\
577
	 SECONDARY_EXEC_TSC_SCALING |					\
578
	 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |				\
579
	 SECONDARY_EXEC_PT_USE_GPA |					\
580
	 SECONDARY_EXEC_PT_CONCEAL_VMX |				\
581
	 SECONDARY_EXEC_ENABLE_VMFUNC |					\
582
	 SECONDARY_EXEC_BUS_LOCK_DETECTION |				\
583
	 SECONDARY_EXEC_NOTIFY_VM_EXITING |				\
584
	 SECONDARY_EXEC_ENCLS_EXITING |					\
585
	 SECONDARY_EXEC_EPT_VIOLATION_VE)
586

587
#define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0
588
#define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL			\
589
	(TERTIARY_EXEC_IPI_VIRT)
590

591
#define BUILD_CONTROLS_SHADOW(lname, uname, bits)						\
592
static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val)			\
593
{												\
594
	if (vmx->loaded_vmcs->controls_shadow.lname != val) {					\
595
		vmcs_write##bits(uname, val);							\
596
		vmx->loaded_vmcs->controls_shadow.lname = val;					\
597
	}											\
598
}												\
599
static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs)			\
600
{												\
601
	return vmcs->controls_shadow.lname;							\
602
}												\
603
static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx)				\
604
{												\
605
	return __##lname##_controls_get(vmx->loaded_vmcs);					\
606
}												\
607
static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val)		\
608
{												\
609
	BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname)));		\
610
	lname##_controls_set(vmx, lname##_controls_get(vmx) | val);				\
611
}												\
612
static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val)	\
613
{												\
614
	BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname)));		\
615
	lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);				\
616
}												\
617
static __always_inline void lname##_controls_changebit(struct vcpu_vmx *vmx, u##bits val,	\
618
						       bool set)				\
619
{												\
620
	if (set)										\
621
		lname##_controls_setbit(vmx, val);						\
622
	else											\
623
		lname##_controls_clearbit(vmx, val);						\
624
}
625
BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
626
BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
627
BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
628
BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
629
BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
630
BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
631

632
/*
633
 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
634
 * cache on demand.  Other registers not listed here are synced to
635
 * the cache immediately after VM-Exit.
636
 */
637
#define VMX_REGS_LAZY_LOAD_SET	((1 << VCPU_REGS_RIP) |         \
638
				(1 << VCPU_REGS_RSP) |          \
639
				(1 << VCPU_EXREG_RFLAGS) |      \
640
				(1 << VCPU_EXREG_PDPTR) |       \
641
				(1 << VCPU_EXREG_SEGMENTS) |    \
642
				(1 << VCPU_EXREG_CR0) |         \
643
				(1 << VCPU_EXREG_CR3) |         \
644
				(1 << VCPU_EXREG_CR4) |         \
645
				(1 << VCPU_EXREG_EXIT_INFO_1) | \
646
				(1 << VCPU_EXREG_EXIT_INFO_2))
647

648
static inline unsigned long vmx_l1_guest_owned_cr0_bits(void)
649
{
650
	unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS;
651

652
	/*
653
	 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging
654
	 * in order to construct shadow PTEs with the correct protections.
655
	 * Note!  CR0.WP technically can be passed through to the guest if
656
	 * paging is disabled, but checking CR0.PG would generate a cyclical
657
	 * dependency of sorts due to forcing the caller to ensure CR0 holds
658
	 * the correct value prior to determining which CR0 bits can be owned
659
	 * by L1.  Keep it simple and limit the optimization to EPT.
660
	 */
661
	if (!enable_ept)
662
		bits &= ~X86_CR0_WP;
663
	return bits;
664
}
665

666
static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
667
{
668
	return container_of(kvm, struct kvm_vmx, kvm);
669
}
670

671
static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
672
{
673
	return container_of(vcpu, struct vcpu_vmx, vcpu);
674
}
675

676
void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu);
677
int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
678
void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
679

680
struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
681
void free_vmcs(struct vmcs *vmcs);
682
int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
683
void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
684
void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
685

686
static inline struct vmcs *alloc_vmcs(bool shadow)
687
{
688
	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
689
			      GFP_KERNEL_ACCOUNT);
690
}
691

692
static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
693
{
694
	return secondary_exec_controls_get(vmx) &
695
		SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
696
}
697

698
static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
699
{
700
	if (!enable_ept)
701
		return true;
702

703
	return allow_smaller_maxphyaddr &&
704
	       cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr;
705
}
706

707
static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
708
{
709
	return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
710
	    (secondary_exec_controls_get(to_vmx(vcpu)) &
711
	    SECONDARY_EXEC_UNRESTRICTED_GUEST));
712
}
713

714
bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
715
static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
716
{
717
	return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
718
}
719

720
void dump_vmcs(struct kvm_vcpu *vcpu);
721

722
static inline int vmx_get_instr_info_reg(u32 vmx_instr_info)
723
{
724
	return (vmx_instr_info >> 3) & 0xf;
725
}
726

727
static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
728
{
729
	return (vmx_instr_info >> 28) & 0xf;
730
}
731

732
static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu)
733
{
734
	return  lapic_in_kernel(vcpu) && enable_ipiv;
735
}
736

737
static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
738
{
739
	vmx->segment_cache.bitmask = 0;
740
}
741

742
int vmx_init(void);
743
void vmx_exit(void);
744

745
#endif /* __KVM_X86_VMX_H */
746

747