1
/* SPDX-License-Identifier: GPL-2.0 */
2
#ifndef ARCH_X86_KVM_X86_H
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#define ARCH_X86_KVM_X86_H
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5
#include <linux/kvm_host.h>
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#include <asm/fpu/xstate.h>
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#include <asm/mce.h>
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#include <asm/pvclock.h>
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#include "kvm_cache_regs.h"
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#include "kvm_emulate.h"
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#include "cpuid.h"
12

13
#define KVM_MAX_MCE_BANKS 32
14

15
struct kvm_caps {
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	/* control of guest tsc rate supported? */
17
	bool has_tsc_control;
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	/* maximum supported tsc_khz for guests */
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	u32  max_guest_tsc_khz;
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	/* number of bits of the fractional part of the TSC scaling ratio */
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	u8   tsc_scaling_ratio_frac_bits;
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	/* maximum allowed value of TSC scaling ratio */
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	u64  max_tsc_scaling_ratio;
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	/* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */
25
	u64  default_tsc_scaling_ratio;
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	/* bus lock detection supported? */
27
	bool has_bus_lock_exit;
28
	/* notify VM exit supported? */
29
	bool has_notify_vmexit;
30
	/* bit mask of VM types */
31
	u32 supported_vm_types;
32

33
	u64 supported_mce_cap;
34
	u64 supported_xcr0;
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	u64 supported_xss;
36
	u64 supported_perf_cap;
37

38
	u64 supported_quirks;
39
	u64 inapplicable_quirks;
40
};
41

42
struct kvm_host_values {
43
	/*
44
	 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical
45
	 * address bits irrespective of features that repurpose legal bits,
46
	 * e.g. MKTME.
47
	 */
48
	u8 maxphyaddr;
49

50
	u64 efer;
51
	u64 xcr0;
52
	u64 xss;
53
	u64 s_cet;
54
	u64 arch_capabilities;
55
};
56

57
void kvm_spurious_fault(void);
58

59
#define SIZE_OF_MEMSLOTS_HASHTABLE \
60
	(sizeof(((struct kvm_memslots *)0)->id_hash) * 2 * KVM_MAX_NR_ADDRESS_SPACES)
61

62
/* Sanity check the size of the memslot hash tables. */
63
static_assert(SIZE_OF_MEMSLOTS_HASHTABLE ==
64
	      (1024 * (1 + IS_ENABLED(CONFIG_X86_64)) * (1 + IS_ENABLED(CONFIG_KVM_SMM))));
65

66
/*
67
 * Assert that "struct kvm_{svm,vmx,tdx}" is an order-0 or order-1 allocation.
68
 * Spilling over to an order-2 allocation isn't fundamentally problematic, but
69
 * isn't expected to happen in the foreseeable future (O(years)).  Assert that
70
 * the size is an order-0 allocation when ignoring the memslot hash tables, to
71
 * help detect and debug unexpected size increases.
72
 */
73
#define KVM_SANITY_CHECK_VM_STRUCT_SIZE(x)						\
74
do {											\
75
	BUILD_BUG_ON(get_order(sizeof(struct x) - SIZE_OF_MEMSLOTS_HASHTABLE) &&	\
76
		     !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN));	\
77
	BUILD_BUG_ON(get_order(sizeof(struct x)) > 1 &&					\
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		     !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN));	\
79
} while (0)
80

81
#define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check)		\
82
({									\
83
	bool failed = (consistency_check);				\
84
	if (failed)							\
85
		trace_kvm_nested_vmenter_failed(#consistency_check, 0);	\
86
	failed;								\
87
})
88

89
/*
90
 * The first...last VMX feature MSRs that are emulated by KVM.  This may or may
91
 * not cover all known VMX MSRs, as KVM doesn't emulate an MSR until there's an
92
 * associated feature that KVM supports for nested virtualization.
93
 */
94
#define KVM_FIRST_EMULATED_VMX_MSR	MSR_IA32_VMX_BASIC
95
#define KVM_LAST_EMULATED_VMX_MSR	MSR_IA32_VMX_VMFUNC
96

97
#define KVM_DEFAULT_PLE_GAP		128
98
#define KVM_VMX_DEFAULT_PLE_WINDOW	4096
99
#define KVM_DEFAULT_PLE_WINDOW_GROW	2
100
#define KVM_DEFAULT_PLE_WINDOW_SHRINK	0
101
#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX	UINT_MAX
102
#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX	USHRT_MAX
103
#define KVM_SVM_DEFAULT_PLE_WINDOW	3000
104

105
/*
106
 * KVM's internal, non-ABI indices for synthetic MSRs. The values themselves
107
 * are arbitrary and have no meaning, the only requirement is that they don't
108
 * conflict with "real" MSRs that KVM supports. Use values at the upper end
109
 * of KVM's reserved paravirtual MSR range to minimize churn, i.e. these values
110
 * will be usable until KVM exhausts its supply of paravirtual MSR indices.
111
 */
112

113
#define MSR_KVM_INTERNAL_GUEST_SSP	0x4b564dff
114

115
static inline unsigned int __grow_ple_window(unsigned int val,
116
		unsigned int base, unsigned int modifier, unsigned int max)
117
{
118
	u64 ret = val;
119

120
	if (modifier < 1)
121
		return base;
122

123
	if (modifier < base)
124
		ret *= modifier;
125
	else
126
		ret += modifier;
127

128
	return min(ret, (u64)max);
129
}
130

131
static inline unsigned int __shrink_ple_window(unsigned int val,
132
		unsigned int base, unsigned int modifier, unsigned int min)
133
{
134
	if (modifier < 1)
135
		return base;
136

137
	if (modifier < base)
138
		val /= modifier;
139
	else
140
		val -= modifier;
141

142
	return max(val, min);
143
}
144

145
#define MSR_IA32_CR_PAT_DEFAULT	\
146
	PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC)
147

148
void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
149
int kvm_check_nested_events(struct kvm_vcpu *vcpu);
150

151
/* Forcibly leave the nested mode in cases like a vCPU reset */
152
static inline void kvm_leave_nested(struct kvm_vcpu *vcpu)
153
{
154
	kvm_x86_ops.nested_ops->leave_nested(vcpu);
155
}
156

157
/*
158
 * If IBRS is advertised to the vCPU, KVM must flush the indirect branch
159
 * predictors when transitioning from L2 to L1, as L1 expects hardware (KVM in
160
 * this case) to provide separate predictor modes.  Bare metal isolates the host
161
 * from the guest, but doesn't isolate different guests from one another (in
162
 * this case L1 and L2). The exception is if bare metal supports same mode IBRS,
163
 * which offers protection within the same mode, and hence protects L1 from L2.
164
 */
165
static inline void kvm_nested_vmexit_handle_ibrs(struct kvm_vcpu *vcpu)
166
{
167
	if (cpu_feature_enabled(X86_FEATURE_AMD_IBRS_SAME_MODE))
168
		return;
169

170
	if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) ||
171
	    guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBRS))
172
		indirect_branch_prediction_barrier();
173
}
174

175
static inline bool kvm_vcpu_has_run(struct kvm_vcpu *vcpu)
176
{
177
	return vcpu->arch.last_vmentry_cpu != -1;
178
}
179

180
static inline void kvm_set_mp_state(struct kvm_vcpu *vcpu, int mp_state)
181
{
182
	vcpu->arch.mp_state = mp_state;
183
	if (mp_state == KVM_MP_STATE_RUNNABLE)
184
		vcpu->arch.pv.pv_unhalted = false;
185
}
186

187
static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu)
188
{
189
	return vcpu->arch.exception.pending ||
190
	       vcpu->arch.exception_vmexit.pending ||
191
	       kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
192
}
193

194
static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
195
{
196
	vcpu->arch.exception.pending = false;
197
	vcpu->arch.exception.injected = false;
198
	vcpu->arch.exception_vmexit.pending = false;
199
}
200

201
static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
202
	bool soft)
203
{
204
	vcpu->arch.interrupt.injected = true;
205
	vcpu->arch.interrupt.soft = soft;
206
	vcpu->arch.interrupt.nr = vector;
207
}
208

209
static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
210
{
211
	vcpu->arch.interrupt.injected = false;
212
}
213

214
static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
215
{
216
	return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
217
		vcpu->arch.nmi_injected;
218
}
219

220
static inline bool kvm_exception_is_soft(unsigned int nr)
221
{
222
	return (nr == BP_VECTOR) || (nr == OF_VECTOR);
223
}
224

225
static inline bool is_protmode(struct kvm_vcpu *vcpu)
226
{
227
	return kvm_is_cr0_bit_set(vcpu, X86_CR0_PE);
228
}
229

230
static inline bool is_long_mode(struct kvm_vcpu *vcpu)
231
{
232
#ifdef CONFIG_X86_64
233
	return !!(vcpu->arch.efer & EFER_LMA);
234
#else
235
	return false;
236
#endif
237
}
238

239
static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
240
{
241
	int cs_db, cs_l;
242

243
	WARN_ON_ONCE(vcpu->arch.guest_state_protected);
244

245
	if (!is_long_mode(vcpu))
246
		return false;
247
	kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
248
	return cs_l;
249
}
250

251
static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu)
252
{
253
	/*
254
	 * If running with protected guest state, the CS register is not
255
	 * accessible. The hypercall register values will have had to been
256
	 * provided in 64-bit mode, so assume the guest is in 64-bit.
257
	 */
258
	return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu);
259
}
260

261
static inline bool x86_exception_has_error_code(unsigned int vector)
262
{
263
	static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
264
			BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
265
			BIT(PF_VECTOR) | BIT(AC_VECTOR);
266

267
	return (1U << vector) & exception_has_error_code;
268
}
269

270
static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
271
{
272
	return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
273
}
274

275
static inline bool is_pae(struct kvm_vcpu *vcpu)
276
{
277
	return kvm_is_cr4_bit_set(vcpu, X86_CR4_PAE);
278
}
279

280
static inline bool is_pse(struct kvm_vcpu *vcpu)
281
{
282
	return kvm_is_cr4_bit_set(vcpu, X86_CR4_PSE);
283
}
284

285
static inline bool is_paging(struct kvm_vcpu *vcpu)
286
{
287
	return likely(kvm_is_cr0_bit_set(vcpu, X86_CR0_PG));
288
}
289

290
static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
291
{
292
	return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
293
}
294

295
static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
296
{
297
	return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48;
298
}
299

300
static inline u8 max_host_virt_addr_bits(void)
301
{
302
	return kvm_cpu_cap_has(X86_FEATURE_LA57) ? 57 : 48;
303
}
304

305
/*
306
 * x86 MSRs which contain linear addresses, x86 hidden segment bases, and
307
 * IDT/GDT bases have static canonicality checks, the size of which depends
308
 * only on the CPU's support for 5-level paging, rather than on the state of
309
 * CR4.LA57.  This applies to both WRMSR and to other instructions that set
310
 * their values, e.g. SGDT.
311
 *
312
 * KVM passes through most of these MSRS and also doesn't intercept the
313
 * instructions that set the hidden segment bases.
314
 *
315
 * Because of this, to be consistent with hardware, even if the guest doesn't
316
 * have LA57 enabled in its CPUID, perform canonicality checks based on *host*
317
 * support for 5 level paging.
318
 *
319
 * Finally, instructions which are related to MMU invalidation of a given
320
 * linear address, also have a similar static canonical check on address.
321
 * This allows for example to invalidate 5-level addresses of a guest from a
322
 * host which uses 4-level paging.
323
 */
324
static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu,
325
					   unsigned int flags)
326
{
327
	if (flags & (X86EMUL_F_INVLPG | X86EMUL_F_MSR | X86EMUL_F_DT_LOAD))
328
		return !__is_canonical_address(la, max_host_virt_addr_bits());
329
	else
330
		return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu));
331
}
332

333
static inline bool is_noncanonical_msr_address(u64 la, struct kvm_vcpu *vcpu)
334
{
335
	return is_noncanonical_address(la, vcpu, X86EMUL_F_MSR);
336
}
337

338
static inline bool is_noncanonical_base_address(u64 la, struct kvm_vcpu *vcpu)
339
{
340
	return is_noncanonical_address(la, vcpu, X86EMUL_F_DT_LOAD);
341
}
342

343
static inline bool is_noncanonical_invlpg_address(u64 la, struct kvm_vcpu *vcpu)
344
{
345
	return is_noncanonical_address(la, vcpu, X86EMUL_F_INVLPG);
346
}
347

348
static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
349
					gva_t gva, gfn_t gfn, unsigned access)
350
{
351
	u64 gen = kvm_memslots(vcpu->kvm)->generation;
352

353
	if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
354
		return;
355

356
	/*
357
	 * If this is a shadow nested page table, the "GVA" is
358
	 * actually a nGPA.
359
	 */
360
	vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
361
	vcpu->arch.mmio_access = access;
362
	vcpu->arch.mmio_gfn = gfn;
363
	vcpu->arch.mmio_gen = gen;
364
}
365

366
static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
367
{
368
	return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
369
}
370

371
/*
372
 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
373
 * clear all mmio cache info.
374
 */
375
#define MMIO_GVA_ANY (~(gva_t)0)
376

377
static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
378
{
379
	if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
380
		return;
381

382
	vcpu->arch.mmio_gva = 0;
383
}
384

385
static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
386
{
387
	if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
388
	      vcpu->arch.mmio_gva == (gva & PAGE_MASK))
389
		return true;
390

391
	return false;
392
}
393

394
static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
395
{
396
	if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
397
	      vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
398
		return true;
399

400
	return false;
401
}
402

403
static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
404
{
405
	unsigned long val = kvm_register_read_raw(vcpu, reg);
406

407
	return is_64_bit_mode(vcpu) ? val : (u32)val;
408
}
409

410
static inline void kvm_register_write(struct kvm_vcpu *vcpu,
411
				       int reg, unsigned long val)
412
{
413
	if (!is_64_bit_mode(vcpu))
414
		val = (u32)val;
415
	return kvm_register_write_raw(vcpu, reg, val);
416
}
417

418
static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
419
{
420
	return !(kvm->arch.disabled_quirks & quirk);
421
}
422

423
void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
424

425
u64 get_kvmclock_ns(struct kvm *kvm);
426
uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm);
427
bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp);
428
int kvm_guest_time_update(struct kvm_vcpu *v);
429

430
int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
431
	gva_t addr, void *val, unsigned int bytes,
432
	struct x86_exception *exception);
433

434
int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
435
	gva_t addr, void *val, unsigned int bytes,
436
	struct x86_exception *exception);
437

438
int handle_ud(struct kvm_vcpu *vcpu);
439

440
void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
441
				   struct kvm_queued_exception *ex);
442

443
int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
444
int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
445
void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
446
int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
447
				    void *insn, int insn_len);
448
int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
449
			    int emulation_type, void *insn, int insn_len);
450
fastpath_t handle_fastpath_wrmsr(struct kvm_vcpu *vcpu);
451
fastpath_t handle_fastpath_wrmsr_imm(struct kvm_vcpu *vcpu, u32 msr, int reg);
452
fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu);
453
fastpath_t handle_fastpath_invd(struct kvm_vcpu *vcpu);
454

455
extern struct kvm_caps kvm_caps;
456
extern struct kvm_host_values kvm_host;
457

458
extern bool enable_pmu;
459

460
/*
461
 * Get a filtered version of KVM's supported XCR0 that strips out dynamic
462
 * features for which the current process doesn't (yet) have permission to use.
463
 * This is intended to be used only when enumerating support to userspace,
464
 * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to be
465
 * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if
466
 * userspace attempts to enable unpermitted features.
467
 */
468
static inline u64 kvm_get_filtered_xcr0(void)
469
{
470
	u64 permitted_xcr0 = kvm_caps.supported_xcr0;
471

472
	BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
473

474
	if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) {
475
		permitted_xcr0 &= xstate_get_guest_group_perm();
476

477
		/*
478
		 * Treat XTILE_CFG as unsupported if the current process isn't
479
		 * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in
480
		 * XCR0 without setting XTILE_DATA is architecturally illegal.
481
		 */
482
		if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA))
483
			permitted_xcr0 &= ~XFEATURE_MASK_XTILE_CFG;
484
	}
485
	return permitted_xcr0;
486
}
487

488
static inline bool kvm_mpx_supported(void)
489
{
490
	return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
491
		== (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
492
}
493

494
extern unsigned int min_timer_period_us;
495

496
extern bool enable_vmware_backdoor;
497

498
extern int pi_inject_timer;
499

500
extern bool report_ignored_msrs;
501

502
extern bool eager_page_split;
503

504
static inline void kvm_pr_unimpl_wrmsr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
505
{
506
	if (report_ignored_msrs)
507
		vcpu_unimpl(vcpu, "Unhandled WRMSR(0x%x) = 0x%llx\n", msr, data);
508
}
509

510
static inline void kvm_pr_unimpl_rdmsr(struct kvm_vcpu *vcpu, u32 msr)
511
{
512
	if (report_ignored_msrs)
513
		vcpu_unimpl(vcpu, "Unhandled RDMSR(0x%x)\n", msr);
514
}
515

516
static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
517
{
518
	return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
519
				   vcpu->arch.virtual_tsc_shift);
520
}
521

522
/* Same "calling convention" as do_div:
523
 * - divide (n << 32) by base
524
 * - put result in n
525
 * - return remainder
526
 */
527
#define do_shl32_div32(n, base)					\
528
	({							\
529
	    u32 __quot, __rem;					\
530
	    asm("divl %2" : "=a" (__quot), "=d" (__rem)		\
531
			: "rm" (base), "0" (0), "1" ((u32) n));	\
532
	    n = __quot;						\
533
	    __rem;						\
534
	 })
535

536
static inline void kvm_disable_exits(struct kvm *kvm, u64 mask)
537
{
538
	kvm->arch.disabled_exits |= mask;
539
}
540

541
static inline bool kvm_mwait_in_guest(struct kvm *kvm)
542
{
543
	return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_MWAIT;
544
}
545

546
static inline bool kvm_hlt_in_guest(struct kvm *kvm)
547
{
548
	return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_HLT;
549
}
550

551
static inline bool kvm_pause_in_guest(struct kvm *kvm)
552
{
553
	return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_PAUSE;
554
}
555

556
static inline bool kvm_cstate_in_guest(struct kvm *kvm)
557
{
558
	return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_CSTATE;
559
}
560

561
static inline bool kvm_aperfmperf_in_guest(struct kvm *kvm)
562
{
563
	return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_APERFMPERF;
564
}
565

566
static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm)
567
{
568
	return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED;
569
}
570

571
static __always_inline void kvm_before_interrupt(struct kvm_vcpu *vcpu,
572
						 enum kvm_intr_type intr)
573
{
574
	WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr);
575
}
576

577
static __always_inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
578
{
579
	WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0);
580
}
581

582
static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu)
583
{
584
	return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI;
585
}
586

587
static inline bool kvm_pat_valid(u64 data)
588
{
589
	if (data & 0xF8F8F8F8F8F8F8F8ull)
590
		return false;
591
	/* 0, 1, 4, 5, 6, 7 are valid values.  */
592
	return (data | ((data & 0x0202020202020202ull) << 1)) == data;
593
}
594

595
static inline bool kvm_dr7_valid(u64 data)
596
{
597
	/* Bits [63:32] are reserved */
598
	return !(data >> 32);
599
}
600
static inline bool kvm_dr6_valid(u64 data)
601
{
602
	/* Bits [63:32] are reserved */
603
	return !(data >> 32);
604
}
605

606
/*
607
 * Trigger machine check on the host. We assume all the MSRs are already set up
608
 * by the CPU and that we still run on the same CPU as the MCE occurred on.
609
 * We pass a fake environment to the machine check handler because we want
610
 * the guest to be always treated like user space, no matter what context
611
 * it used internally.
612
 */
613
static inline void kvm_machine_check(void)
614
{
615
#if defined(CONFIG_X86_MCE)
616
	struct pt_regs regs = {
617
		.cs = 3, /* Fake ring 3 no matter what the guest ran on */
618
		.flags = X86_EFLAGS_IF,
619
	};
620

621
	do_machine_check(&regs);
622
#endif
623
}
624

625
void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
626
void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
627
int kvm_spec_ctrl_test_value(u64 value);
628
int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
629
			      struct x86_exception *e);
630
int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
631
bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
632

633
enum kvm_msr_access {
634
	MSR_TYPE_R	= BIT(0),
635
	MSR_TYPE_W	= BIT(1),
636
	MSR_TYPE_RW	= MSR_TYPE_R | MSR_TYPE_W,
637
};
638

639
/*
640
 * Internal error codes that are used to indicate that MSR emulation encountered
641
 * an error that should result in #GP in the guest, unless userspace handles it.
642
 * Note, '1', '0', and negative numbers are off limits, as they are used by KVM
643
 * as part of KVM's lightly documented internal KVM_RUN return codes.
644
 *
645
 * UNSUPPORTED	- The MSR isn't supported, either because it is completely
646
 *		  unknown to KVM, or because the MSR should not exist according
647
 *		  to the vCPU model.
648
 *
649
 * FILTERED	- Access to the MSR is denied by a userspace MSR filter.
650
 */
651
#define  KVM_MSR_RET_UNSUPPORTED	2
652
#define  KVM_MSR_RET_FILTERED		3
653

654
static inline bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
655
{
656
	return !(cr4 & vcpu->arch.cr4_guest_rsvd_bits);
657
}
658

659
#define __cr4_reserved_bits(__cpu_has, __c)             \
660
({                                                      \
661
	u64 __reserved_bits = CR4_RESERVED_BITS;        \
662
                                                        \
663
	if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
664
		__reserved_bits |= X86_CR4_OSXSAVE;     \
665
	if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
666
		__reserved_bits |= X86_CR4_SMEP;        \
667
	if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
668
		__reserved_bits |= X86_CR4_SMAP;        \
669
	if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
670
		__reserved_bits |= X86_CR4_FSGSBASE;    \
671
	if (!__cpu_has(__c, X86_FEATURE_PKU))           \
672
		__reserved_bits |= X86_CR4_PKE;         \
673
	if (!__cpu_has(__c, X86_FEATURE_LA57))          \
674
		__reserved_bits |= X86_CR4_LA57;        \
675
	if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
676
		__reserved_bits |= X86_CR4_UMIP;        \
677
	if (!__cpu_has(__c, X86_FEATURE_VMX))           \
678
		__reserved_bits |= X86_CR4_VMXE;        \
679
	if (!__cpu_has(__c, X86_FEATURE_PCID))          \
680
		__reserved_bits |= X86_CR4_PCIDE;       \
681
	if (!__cpu_has(__c, X86_FEATURE_LAM))           \
682
		__reserved_bits |= X86_CR4_LAM_SUP;     \
683
	if (!__cpu_has(__c, X86_FEATURE_SHSTK) &&       \
684
	    !__cpu_has(__c, X86_FEATURE_IBT))           \
685
		__reserved_bits |= X86_CR4_CET;         \
686
	__reserved_bits;                                \
687
})
688

689
int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
690
			  void *dst);
691
int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
692
			 void *dst);
693
int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
694
			 unsigned int port, void *data,  unsigned int count,
695
			 int in);
696

697
static inline bool user_exit_on_hypercall(struct kvm *kvm, unsigned long hc_nr)
698
{
699
	return kvm->arch.hypercall_exit_enabled & BIT(hc_nr);
700
}
701

702
int ____kvm_emulate_hypercall(struct kvm_vcpu *vcpu, int cpl,
703
			      int (*complete_hypercall)(struct kvm_vcpu *));
704

705
#define __kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall)			\
706
({										\
707
	int __ret;								\
708
	__ret = ____kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall);	\
709
										\
710
	if (__ret > 0)								\
711
		__ret = complete_hypercall(_vcpu);				\
712
	__ret;									\
713
})
714

715
int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
716

717
#define CET_US_RESERVED_BITS		GENMASK(9, 6)
718
#define CET_US_SHSTK_MASK_BITS		GENMASK(1, 0)
719
#define CET_US_IBT_MASK_BITS		(GENMASK_ULL(5, 2) | GENMASK_ULL(63, 10))
720
#define CET_US_LEGACY_BITMAP_BASE(data)	((data) >> 12)
721

722
static inline bool kvm_is_valid_u_s_cet(struct kvm_vcpu *vcpu, u64 data)
723
{
724
	if (data & CET_US_RESERVED_BITS)
725
		return false;
726
	if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK) &&
727
	    (data & CET_US_SHSTK_MASK_BITS))
728
		return false;
729
	if (!guest_cpu_cap_has(vcpu, X86_FEATURE_IBT) &&
730
	    (data & CET_US_IBT_MASK_BITS))
731
		return false;
732
	if (!IS_ALIGNED(CET_US_LEGACY_BITMAP_BASE(data), 4))
733
		return false;
734
	/* IBT can be suppressed iff the TRACKER isn't WAIT_ENDBR. */
735
	if ((data & CET_SUPPRESS) && (data & CET_WAIT_ENDBR))
736
		return false;
737

738
	return true;
739
}
740
#endif
741

742