1
// SPDX-License-Identifier: GPL-2.0
2
/*
3
 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
4
 */
5

6
#include <linux/bitfield.h>
7
#include <linux/delay.h>
8
#include <linux/dmi.h>
9
#include <linux/pci.h>
10
#include <linux/suspend.h>
11
#include <linux/vgaarb.h>
12
#include <asm/amd/node.h>
13
#include <asm/hpet.h>
14
#include <asm/pci_x86.h>
15

16
static void pci_fixup_i450nx(struct pci_dev *d)
17
{
18
	/*
19
	 * i450NX -- Find and scan all secondary buses on all PXB's.
20
	 */
21
	int pxb, reg;
22
	u8 busno, suba, subb;
23

24
	dev_warn(&d->dev, "Searching for i450NX host bridges\n");
25
	reg = 0xd0;
26
	for(pxb = 0; pxb < 2; pxb++) {
27
		pci_read_config_byte(d, reg++, &busno);
28
		pci_read_config_byte(d, reg++, &suba);
29
		pci_read_config_byte(d, reg++, &subb);
30
		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
31
			suba, subb);
32
		if (busno)
33
			pcibios_scan_root(busno);	/* Bus A */
34
		if (suba < subb)
35
			pcibios_scan_root(suba+1);	/* Bus B */
36
	}
37
	pcibios_last_bus = -1;
38
}
39
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
40

41
static void pci_fixup_i450gx(struct pci_dev *d)
42
{
43
	/*
44
	 * i450GX and i450KX -- Find and scan all secondary buses.
45
	 * (called separately for each PCI bridge found)
46
	 */
47
	u8 busno;
48
	pci_read_config_byte(d, 0x4a, &busno);
49
	dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
50
	pcibios_scan_root(busno);
51
	pcibios_last_bus = -1;
52
}
53
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
54

55
static void pci_fixup_umc_ide(struct pci_dev *d)
56
{
57
	/*
58
	 * UM8886BF IDE controller sets region type bits incorrectly,
59
	 * therefore they look like memory despite of them being I/O.
60
	 */
61
	int i;
62

63
	dev_warn(&d->dev, "Fixing base address flags\n");
64
	for(i = 0; i < 4; i++)
65
		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
66
}
67
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
68

69
static void pci_fixup_latency(struct pci_dev *d)
70
{
71
	/*
72
	 *  SiS 5597 and 5598 chipsets require latency timer set to
73
	 *  at most 32 to avoid lockups.
74
	 */
75
	dev_dbg(&d->dev, "Setting max latency to 32\n");
76
	pcibios_max_latency = 32;
77
}
78
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
79
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
80

81
static void pci_fixup_piix4_acpi(struct pci_dev *d)
82
{
83
	/*
84
	 * PIIX4 ACPI device: hardwired IRQ9
85
	 */
86
	d->irq = 9;
87
}
88
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
89

90
/*
91
 * Addresses issues with problems in the memory write queue timer in
92
 * certain VIA Northbridges.  This bugfix is per VIA's specifications,
93
 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
94
 * to trigger a bug in its integrated ProSavage video card, which
95
 * causes screen corruption.  We only clear bits 6 and 7 for that chipset,
96
 * until VIA can provide us with definitive information on why screen
97
 * corruption occurs, and what exactly those bits do.
98
 *
99
 * VIA 8363,8622,8361 Northbridges:
100
 *  - bits  5, 6, 7 at offset 0x55 need to be turned off
101
 * VIA 8367 (KT266x) Northbridges:
102
 *  - bits  5, 6, 7 at offset 0x95 need to be turned off
103
 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
104
 *  - bits     6, 7 at offset 0x55 need to be turned off
105
 */
106

107
#define VIA_8363_KL133_REVISION_ID 0x81
108
#define VIA_8363_KM133_REVISION_ID 0x84
109

110
static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
111
{
112
	u8 v;
113
	int where = 0x55;
114
	int mask = 0x1f; /* clear bits 5, 6, 7 by default */
115

116
	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
117
		/* fix pci bus latency issues resulted by NB bios error
118
		   it appears on bug free^Wreduced kt266x's bios forces
119
		   NB latency to zero */
120
		pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
121

122
		where = 0x95; /* the memory write queue timer register is
123
				different for the KT266x's: 0x95 not 0x55 */
124
	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
125
			(d->revision == VIA_8363_KL133_REVISION_ID ||
126
			d->revision == VIA_8363_KM133_REVISION_ID)) {
127
			mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
128
					causes screen corruption on the KL133/KM133 */
129
	}
130

131
	pci_read_config_byte(d, where, &v);
132
	if (v & ~mask) {
133
		dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
134
			d->device, d->revision, where, v, mask, v & mask);
135
		v &= mask;
136
		pci_write_config_byte(d, where, v);
137
	}
138
}
139
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
140
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
141
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
142
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
143
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
144
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
145
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
146
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
147

148
/*
149
 * For some reasons Intel decided that certain parts of their
150
 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
151
 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
152
 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
153
 * to Intel terminology. These devices do forward all addresses from
154
 * system to PCI bus no matter what are their window settings, so they are
155
 * "transparent" (or subtractive decoding) from programmers point of view.
156
 */
157
static void pci_fixup_transparent_bridge(struct pci_dev *dev)
158
{
159
	if ((dev->device & 0xff00) == 0x2400)
160
		dev->transparent = 1;
161
}
162
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
163
			 PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
164

165
/*
166
 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
167
 *
168
 * From information provided by "Allen Martin" <[email protected]>:
169
 *
170
 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
171
 * sequence.  Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
172
 * This allows the state-machine and timer to return to a proper state within
173
 * 80 ns of the CONNECT and probe appearing together.  Since the CPU will not
174
 * issue another HALT within 80 ns of the initial HALT, the failure condition
175
 * is avoided.
176
 */
177
static void pci_fixup_nforce2(struct pci_dev *dev)
178
{
179
	u32 val;
180

181
	/*
182
	 * Chip  Old value   New value
183
	 * C17   0x1F0FFF01  0x1F01FF01
184
	 * C18D  0x9F0FFF01  0x9F01FF01
185
	 *
186
	 * Northbridge chip version may be determined by
187
	 * reading the PCI revision ID (0xC1 or greater is C18D).
188
	 */
189
	pci_read_config_dword(dev, 0x6c, &val);
190

191
	/*
192
	 * Apply fixup if needed, but don't touch disconnect state
193
	 */
194
	if ((val & 0x00FF0000) != 0x00010000) {
195
		dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
196
		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
197
	}
198
}
199
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
200
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
201

202
/* Max PCI Express root ports */
203
#define MAX_PCIEROOT	6
204
static int quirk_aspm_offset[MAX_PCIEROOT << 3];
205

206
#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
207

208
static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
209
{
210
	return raw_pci_read(pci_domain_nr(bus), bus->number,
211
						devfn, where, size, value);
212
}
213

214
/*
215
 * Replace the original pci bus ops for write with a new one that will filter
216
 * the request to insure ASPM cannot be enabled.
217
 */
218
static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
219
{
220
	u8 offset;
221

222
	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
223

224
	if ((offset) && (where == offset))
225
		value = value & ~PCI_EXP_LNKCTL_ASPMC;
226

227
	return raw_pci_write(pci_domain_nr(bus), bus->number,
228
						devfn, where, size, value);
229
}
230

231
static struct pci_ops quirk_pcie_aspm_ops = {
232
	.read = quirk_pcie_aspm_read,
233
	.write = quirk_pcie_aspm_write,
234
};
235

236
/*
237
 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
238
 *
239
 * Save the register offset, where the ASPM control bits are located,
240
 * for each PCI Express device that is in the device list of
241
 * the root port in an array for fast indexing. Replace the bus ops
242
 * with the modified one.
243
 */
244
static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
245
{
246
	int i;
247
	struct pci_bus  *pbus;
248
	struct pci_dev *dev;
249

250
	if ((pbus = pdev->subordinate) == NULL)
251
		return;
252

253
	/*
254
	 * Check if the DID of pdev matches one of the six root ports. This
255
	 * check is needed in the case this function is called directly by the
256
	 * hot-plug driver.
257
	 */
258
	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
259
	    (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
260
		return;
261

262
	if (list_empty(&pbus->devices)) {
263
		/*
264
		 * If no device is attached to the root port at power-up or
265
		 * after hot-remove, the pbus->devices is empty and this code
266
		 * will set the offsets to zero and the bus ops to parent's bus
267
		 * ops, which is unmodified.
268
		 */
269
		for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
270
			quirk_aspm_offset[i] = 0;
271

272
		pci_bus_set_ops(pbus, pbus->parent->ops);
273
	} else {
274
		/*
275
		 * If devices are attached to the root port at power-up or
276
		 * after hot-add, the code loops through the device list of
277
		 * each root port to save the register offsets and replace the
278
		 * bus ops.
279
		 */
280
		list_for_each_entry(dev, &pbus->devices, bus_list)
281
			/* There are 0 to 8 devices attached to this bus */
282
			quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =
283
				dev->pcie_cap + PCI_EXP_LNKCTL;
284

285
		pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops);
286
		dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");
287
	}
288

289
}
290
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA,	pcie_rootport_aspm_quirk);
291
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA1,	pcie_rootport_aspm_quirk);
292
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB,	pcie_rootport_aspm_quirk);
293
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB1,	pcie_rootport_aspm_quirk);
294
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC,	pcie_rootport_aspm_quirk);
295
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC1,	pcie_rootport_aspm_quirk);
296

297
/*
298
 * PCIe devices underneath Xeon 6 PCIe Root Port bifurcated to x2 have lower
299
 * performance with Extended Tags and MRRS > 128B. Work around the performance
300
 * problems by disabling Extended Tags and limiting MRRS to 128B.
301
 *
302
 * https://cdrdv2.intel.com/v1/dl/getContent/837176
303
 */
304
static int limit_mrrs_to_128(struct pci_host_bridge *b, struct pci_dev *pdev)
305
{
306
	int readrq = pcie_get_readrq(pdev);
307

308
	if (readrq > 128)
309
		pcie_set_readrq(pdev, 128);
310

311
	return 0;
312
}
313

314
static void pci_xeon_x2_bifurc_quirk(struct pci_dev *pdev)
315
{
316
	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
317
	u32 linkcap;
318

319
	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &linkcap);
320
	if (FIELD_GET(PCI_EXP_LNKCAP_MLW, linkcap) != 0x2)
321
		return;
322

323
	bridge->no_ext_tags = 1;
324
	bridge->enable_device = limit_mrrs_to_128;
325
	pci_info(pdev, "Disabling Extended Tags and limiting MRRS to 128B (performance reasons due to x2 PCIe link)\n");
326
}
327

328
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db0, pci_xeon_x2_bifurc_quirk);
329
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db1, pci_xeon_x2_bifurc_quirk);
330
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db2, pci_xeon_x2_bifurc_quirk);
331
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db3, pci_xeon_x2_bifurc_quirk);
332
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db6, pci_xeon_x2_bifurc_quirk);
333
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db7, pci_xeon_x2_bifurc_quirk);
334
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db8, pci_xeon_x2_bifurc_quirk);
335
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0db9, pci_xeon_x2_bifurc_quirk);
336

337
/*
338
 * Fixup to mark boot BIOS video selected by BIOS before it changes
339
 *
340
 * From information provided by "Jon Smirl" <[email protected]>
341
 *
342
 * The standard boot ROM sequence for an x86 machine uses the BIOS
343
 * to select an initial video card for boot display. This boot video
344
 * card will have its BIOS copied to 0xC0000 in system RAM.
345
 * IORESOURCE_ROM_SHADOW is used to associate the boot video
346
 * card with this copy. On laptops this copy has to be used since
347
 * the main ROM may be compressed or combined with another image.
348
 * See pci_map_rom() for use of this flag. Before marking the device
349
 * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
350
 * by either arch code or vga-arbitration; if so only apply the fixup to this
351
 * already-determined primary video card.
352
 */
353

354
static void pci_fixup_video(struct pci_dev *pdev)
355
{
356
	struct pci_dev *bridge;
357
	struct pci_bus *bus;
358
	u16 config;
359
	struct resource *res;
360

361
	/* Is VGA routed to us? */
362
	bus = pdev->bus;
363
	while (bus) {
364
		bridge = bus->self;
365

366
		/*
367
		 * From information provided by
368
		 * "David Miller" <[email protected]>
369
		 * The bridge control register is valid for PCI header
370
		 * type BRIDGE, or CARDBUS. Host to PCI controllers use
371
		 * PCI header type NORMAL.
372
		 */
373
		if (bridge && (pci_is_bridge(bridge))) {
374
			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
375
						&config);
376
			if (!(config & PCI_BRIDGE_CTL_VGA))
377
				return;
378
		}
379
		bus = bus->parent;
380
	}
381
	if (!vga_default_device() || pdev == vga_default_device()) {
382
		pci_read_config_word(pdev, PCI_COMMAND, &config);
383
		if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
384
			res = &pdev->resource[PCI_ROM_RESOURCE];
385

386
			pci_disable_rom(pdev);
387
			if (res->parent)
388
				release_resource(res);
389

390
			res->start = 0xC0000;
391
			res->end = res->start + 0x20000 - 1;
392
			res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
393
				     IORESOURCE_PCI_FIXED;
394
			dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
395
				 res);
396
		}
397
	}
398
}
399
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_ANY_ID, PCI_ANY_ID,
400
			       PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
401

402

403
static const struct dmi_system_id msi_k8t_dmi_table[] = {
404
	{
405
		.ident = "MSI-K8T-Neo2Fir",
406
		.matches = {
407
			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
408
			DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
409
		},
410
	},
411
	{}
412
};
413

414
/*
415
 * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
416
 * card if a PCI-soundcard is added.
417
 *
418
 * The BIOS only gives options "DISABLED" and "AUTO". This code sets
419
 * the corresponding register-value to enable the soundcard.
420
 *
421
 * The soundcard is only enabled, if the mainboard is identified
422
 * via DMI-tables and the soundcard is detected to be off.
423
 */
424
static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
425
{
426
	unsigned char val;
427
	if (!dmi_check_system(msi_k8t_dmi_table))
428
		return; /* only applies to MSI K8T Neo2-FIR */
429

430
	pci_read_config_byte(dev, 0x50, &val);
431
	if (val & 0x40) {
432
		pci_write_config_byte(dev, 0x50, val & (~0x40));
433

434
		/* verify the change for status output */
435
		pci_read_config_byte(dev, 0x50, &val);
436
		if (val & 0x40)
437
			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
438
					"can't enable onboard soundcard!\n");
439
		else
440
			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
441
					"enabled onboard soundcard\n");
442
	}
443
}
444
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
445
		pci_fixup_msi_k8t_onboard_sound);
446
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
447
		pci_fixup_msi_k8t_onboard_sound);
448

449
/*
450
 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
451
 *
452
 * We pretend to bring them out of full D3 state, and restore the proper
453
 * IRQ, PCI cache line size, and BARs, otherwise the device won't function
454
 * properly.  In some cases, the device will generate an interrupt on
455
 * the wrong IRQ line, causing any devices sharing the line it's
456
 * *supposed* to use to be disabled by the kernel's IRQ debug code.
457
 */
458
static u16 toshiba_line_size;
459

460
static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
461
	{
462
		.ident = "Toshiba PS5 based laptop",
463
		.matches = {
464
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
465
			DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
466
		},
467
	},
468
	{
469
		.ident = "Toshiba PSM4 based laptop",
470
		.matches = {
471
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
472
			DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
473
		},
474
	},
475
	{
476
		.ident = "Toshiba A40 based laptop",
477
		.matches = {
478
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
479
			DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
480
		},
481
	},
482
	{ }
483
};
484

485
static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
486
{
487
	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
488
		return; /* only applies to certain Toshibas (so far) */
489

490
	dev->current_state = PCI_D3cold;
491
	pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
492
}
493
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
494
			 pci_pre_fixup_toshiba_ohci1394);
495

496
static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
497
{
498
	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
499
		return; /* only applies to certain Toshibas (so far) */
500

501
	/* Restore config space on Toshiba laptops */
502
	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
503
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
504
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
505
			       pci_resource_start(dev, 0));
506
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
507
			       pci_resource_start(dev, 1));
508
}
509
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
510
			 pci_post_fixup_toshiba_ohci1394);
511

512

513
/*
514
 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
515
 * configuration space.
516
 */
517
static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
518
{
519
	u8 r;
520
	/* clear 'F4 Video Configuration Trap' bit */
521
	pci_read_config_byte(dev, 0x42, &r);
522
	r &= 0xfd;
523
	pci_write_config_byte(dev, 0x42, r);
524
}
525
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
526
			pci_early_fixup_cyrix_5530);
527
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
528
			pci_early_fixup_cyrix_5530);
529

530
/*
531
 * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
532
 * prevent update of the BAR0, which doesn't look like a normal BAR.
533
 */
534
static void pci_siemens_interrupt_controller(struct pci_dev *dev)
535
{
536
	dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
537
}
538
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
539
			  pci_siemens_interrupt_controller);
540

541
/*
542
 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
543
 * confusing the PCI engine:
544
 */
545
static void sb600_disable_hpet_bar(struct pci_dev *dev)
546
{
547
	u8 val;
548

549
	/*
550
	 * The SB600 and SB700 both share the same device
551
	 * ID, but the PM register 0x55 does something different
552
	 * for the SB700, so make sure we are dealing with the
553
	 * SB600 before touching the bit:
554
	 */
555

556
	pci_read_config_byte(dev, 0x08, &val);
557

558
	if (val < 0x2F) {
559
		outb(0x55, 0xCD6);
560
		val = inb(0xCD7);
561

562
		/* Set bit 7 in PM register 0x55 */
563
		outb(0x55, 0xCD6);
564
		outb(val | 0x80, 0xCD7);
565
	}
566
}
567
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
568

569
#ifdef CONFIG_HPET_TIMER
570
static void sb600_hpet_quirk(struct pci_dev *dev)
571
{
572
	struct resource *r = &dev->resource[1];
573

574
	if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {
575
		r->flags |= IORESOURCE_PCI_FIXED;
576
		dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");
577
	}
578
}
579
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk);
580
#endif
581

582
/*
583
 * Twinhead H12Y needs us to block out a region otherwise we map devices
584
 * there and any access kills the box.
585
 *
586
 *   See: https://bugzilla.kernel.org/show_bug.cgi?id=10231
587
 *
588
 * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
589
 */
590
static void twinhead_reserve_killing_zone(struct pci_dev *dev)
591
{
592
        if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
593
                pr_info("Reserving memory on Twinhead H12Y\n");
594
                request_mem_region(0xFFB00000, 0x100000, "twinhead");
595
        }
596
}
597
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
598

599
/*
600
 * Device [8086:2fc0]
601
 * Erratum HSE43
602
 * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset
603
 * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
604
 *
605
 * Devices [8086:6f60,6fa0,6fc0]
606
 * Erratum BDF2
607
 * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
608
 * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
609
 */
610
static void pci_invalid_bar(struct pci_dev *dev)
611
{
612
	dev->non_compliant_bars = 1;
613
}
614
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar);
615
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar);
616
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar);
617
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar);
618
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ec, pci_invalid_bar);
619
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ed, pci_invalid_bar);
620
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26c, pci_invalid_bar);
621
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26d, pci_invalid_bar);
622

623
/*
624
 * Device [1022:7808]
625
 * 23. USB Wake on Connect/Disconnect with Low Speed Devices
626
 * https://support.amd.com/TechDocs/46837.pdf
627
 * Appendix A2
628
 * https://support.amd.com/TechDocs/42413.pdf
629
 */
630
static void pci_fixup_amd_ehci_pme(struct pci_dev *dev)
631
{
632
	dev_info(&dev->dev, "PME# does not work under D3, disabling it\n");
633
	dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold)
634
		>> PCI_PM_CAP_PME_SHIFT);
635
}
636
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);
637

638
/*
639
 * Device [1022:7914]
640
 * When in D0, PME# doesn't get asserted when plugging USB 2.0 device.
641
 */
642
static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev)
643
{
644
	dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");
645
	dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
646
}
647
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);
648

649
/*
650
 * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
651
 *
652
 * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to
653
 * the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used
654
 * for soft poweroff and suspend-to-RAM.
655
 *
656
 * As far as we know, this is related to the address space, not to the Root
657
 * Port itself.  Attaching the quirk to the Root Port is a convenience, but
658
 * it could probably also be a standalone DMI quirk.
659
 *
660
 * https://bugzilla.kernel.org/show_bug.cgi?id=103211
661
 */
662
static void quirk_apple_mbp_poweroff(struct pci_dev *pdev)
663
{
664
	struct device *dev = &pdev->dev;
665
	struct resource *res;
666

667
	if ((!dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,4") &&
668
	     !dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,5")) ||
669
	    pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x1c, 0))
670
		return;
671

672
	res = request_mem_region(0x7fa00000, 0x200000,
673
				 "MacBook Pro poweroff workaround");
674
	if (res)
675
		dev_info(dev, "claimed %s %pR\n", res->name, res);
676
	else
677
		dev_info(dev, "can't work around MacBook Pro poweroff issue\n");
678
}
679
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
680

681
/*
682
 * VMD-enabled root ports will change the source ID for all messages
683
 * to the VMD device. Rather than doing device matching with the source
684
 * ID, the AER driver should traverse the child device tree, reading
685
 * AER registers to find the faulting device.
686
 */
687
static void quirk_no_aersid(struct pci_dev *pdev)
688
{
689
	/* VMD Domain */
690
	if (is_vmd(pdev->bus) && pci_is_root_bus(pdev->bus))
691
		pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
692
}
693
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
694
			      PCI_CLASS_BRIDGE_PCI, 8, quirk_no_aersid);
695

696
static void quirk_intel_th_dnv(struct pci_dev *dev)
697
{
698
	struct resource *r = &dev->resource[4];
699

700
	/*
701
	 * Denverton reports 2k of RTIT_BAR (intel_th resource 4), which
702
	 * appears to be 4 MB in reality.
703
	 */
704
	if (r->end == r->start + 0x7ff) {
705
		r->start = 0;
706
		r->end   = 0x3fffff;
707
		r->flags |= IORESOURCE_UNSET;
708
	}
709
}
710
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv);
711

712
#ifdef CONFIG_PHYS_ADDR_T_64BIT
713

714
#define AMD_141b_MMIO_BASE(x)	(0x80 + (x) * 0x8)
715
#define AMD_141b_MMIO_BASE_RE_MASK		BIT(0)
716
#define AMD_141b_MMIO_BASE_WE_MASK		BIT(1)
717
#define AMD_141b_MMIO_BASE_MMIOBASE_MASK	GENMASK(31,8)
718

719
#define AMD_141b_MMIO_LIMIT(x)	(0x84 + (x) * 0x8)
720
#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK	GENMASK(31,8)
721

722
#define AMD_141b_MMIO_HIGH(x)	(0x180 + (x) * 0x4)
723
#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK	GENMASK(7,0)
724
#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT	16
725
#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK	GENMASK(23,16)
726

727
/*
728
 * The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow
729
 * configuring host bridge windows using the _PRS and _SRS methods.
730
 *
731
 * But this is rarely implemented, so we manually enable a large 64bit BAR for
732
 * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors
733
 * here.
734
 */
735
static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
736
{
737
	static const char *name = "PCI Bus 0000:00";
738
	struct resource *res, *conflict;
739
	u32 base, limit, high;
740
	struct pci_dev *other;
741
	unsigned i;
742

743
	if (!(pci_probe & PCI_BIG_ROOT_WINDOW))
744
		return;
745

746
	/* Check that we are the only device of that type */
747
	other = pci_get_device(dev->vendor, dev->device, NULL);
748
	if (other != dev ||
749
	    (other = pci_get_device(dev->vendor, dev->device, other))) {
750
		/* This is a multi-socket system, don't touch it for now */
751
		pci_dev_put(other);
752
		return;
753
	}
754

755
	for (i = 0; i < 8; i++) {
756
		pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
757
		pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high);
758

759
		/* Is this slot free? */
760
		if (!(base & (AMD_141b_MMIO_BASE_RE_MASK |
761
			      AMD_141b_MMIO_BASE_WE_MASK)))
762
			break;
763

764
		base >>= 8;
765
		base |= high << 24;
766

767
		/* Abort if a slot already configures a 64bit BAR. */
768
		if (base > 0x10000)
769
			return;
770
	}
771
	if (i == 8)
772
		return;
773

774
	res = kzalloc(sizeof(*res), GFP_KERNEL);
775
	if (!res)
776
		return;
777

778
	/*
779
	 * Allocate a 256GB window directly below the 0xfd00000000 hardware
780
	 * limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6).
781
	 */
782
	res->name = name;
783
	res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
784
		IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
785
	res->start = 0xbd00000000ull;
786
	res->end = 0xfd00000000ull - 1;
787

788
	conflict = request_resource_conflict(&iomem_resource, res);
789
	if (conflict) {
790
		kfree(res);
791
		if (conflict->name != name)
792
			return;
793

794
		/* We are resuming from suspend; just reenable the window */
795
		res = conflict;
796
	} else {
797
		dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
798
			 res);
799
		add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
800
		pci_bus_add_resource(dev->bus, res);
801
	}
802

803
	base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
804
		AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
805
	limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK;
806
	high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) |
807
		((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT)
808
		 & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK);
809

810
	pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
811
	pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
812
	pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
813
}
814
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
815
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
816
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
817
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
818
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
819
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
820
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
821
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
822
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
823
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
824

825
#define RS690_LOWER_TOP_OF_DRAM2	0x30
826
#define RS690_LOWER_TOP_OF_DRAM2_VALID	0x1
827
#define RS690_UPPER_TOP_OF_DRAM2	0x31
828
#define RS690_HTIU_NB_INDEX		0xA8
829
#define RS690_HTIU_NB_INDEX_WR_ENABLE	0x100
830
#define RS690_HTIU_NB_DATA		0xAC
831

832
/*
833
 * Some BIOS implementations support RAM above 4GB, but do not configure the
834
 * PCI host to respond to bus master accesses for these addresses. These
835
 * implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA
836
 * works as expected for addresses below 4GB.
837
 *
838
 * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57)
839
 * https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf
840
 */
841
static void rs690_fix_64bit_dma(struct pci_dev *pdev)
842
{
843
	u32 val = 0;
844
	phys_addr_t top_of_dram = __pa(high_memory - 1) + 1;
845

846
	if (top_of_dram <= (1ULL << 32))
847
		return;
848

849
	pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
850
				RS690_LOWER_TOP_OF_DRAM2);
851
	pci_read_config_dword(pdev, RS690_HTIU_NB_DATA, &val);
852

853
	if (val)
854
		return;
855

856
	pci_info(pdev, "Adjusting top of DRAM to %pa for 64-bit DMA support\n", &top_of_dram);
857

858
	pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
859
		RS690_UPPER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE);
860
	pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, top_of_dram >> 32);
861

862
	pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
863
		RS690_LOWER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE);
864
	pci_write_config_dword(pdev, RS690_HTIU_NB_DATA,
865
		top_of_dram | RS690_LOWER_TOP_OF_DRAM2_VALID);
866
}
867
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
868

869
#endif
870

871
#ifdef CONFIG_AMD_NODE
872

873
#define AMD_15B8_RCC_DEV2_EPF0_STRAP2                                  0x10136008
874
#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK       0x00000080L
875

876
static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
877
{
878
	u32 data;
879

880
	if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) {
881
		data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK;
882
		if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data))
883
			pci_err(dev, "Failed to write data 0x%x\n", data);
884
	} else {
885
		pci_err(dev, "Failed to read data\n");
886
	}
887
}
888
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
889
#endif
890

891
/*
892
 * When returning from D3cold to D0, firmware on some Google Coral and Reef
893
 * family Chromebooks with Intel Apollo Lake SoC clobbers the headers of
894
 * both the L1 PM Substates capability and the previous capability for the
895
 * "Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1".
896
 *
897
 * Save those values at enumeration-time and restore them at resume.
898
 */
899

900
static u16 prev_cap, l1ss_cap;
901
static u32 prev_header, l1ss_header;
902

903
static void chromeos_save_apl_pci_l1ss_capability(struct pci_dev *dev)
904
{
905
	int pos = PCI_CFG_SPACE_SIZE, prev = 0;
906
	u32 header, pheader = 0;
907

908
	while (pos) {
909
		pci_read_config_dword(dev, pos, &header);
910
		if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_L1SS) {
911
			prev_cap = prev;
912
			prev_header = pheader;
913
			l1ss_cap = pos;
914
			l1ss_header = header;
915
			return;
916
		}
917

918
		prev = pos;
919
		pheader = header;
920
		pos = PCI_EXT_CAP_NEXT(header);
921
	}
922
}
923

924
static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev)
925
{
926
	u32 header;
927

928
	if (!prev_cap || !prev_header || !l1ss_cap || !l1ss_header)
929
		return;
930

931
	/* Fixup the header of L1SS Capability if missing */
932
	pci_read_config_dword(dev, l1ss_cap, &header);
933
	if (header != l1ss_header) {
934
		pci_write_config_dword(dev, l1ss_cap, l1ss_header);
935
		pci_info(dev, "restore L1SS Capability header (was %#010x now %#010x)\n",
936
			 header, l1ss_header);
937
	}
938

939
	/* Fixup the link to L1SS Capability if missing */
940
	pci_read_config_dword(dev, prev_cap, &header);
941
	if (header != prev_header) {
942
		pci_write_config_dword(dev, prev_cap, prev_header);
943
		pci_info(dev, "restore previous Capability header (was %#010x now %#010x)\n",
944
			 header, prev_header);
945
	}
946
}
947
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
948
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);
949

950
/*
951
 * Disable D3cold on Asus B1400 PCI-NVMe bridge
952
 *
953
 * On this platform with VMD off, the NVMe device cannot successfully power
954
 * back on from D3cold. This appears to be an untested transition by the
955
 * vendor: Windows leaves the NVMe and parent bridge in D0 during suspend.
956
 *
957
 * We disable D3cold on the parent bridge for simplicity, and the fact that
958
 * both parent bridge and NVMe device share the same power resource.
959
 *
960
 * This is only needed on BIOS versions before 308; the newer versions flip
961
 * StorageD3Enable from 1 to 0.
962
 */
963
static const struct dmi_system_id asus_nvme_broken_d3cold_table[] = {
964
	{
965
		.matches = {
966
				DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
967
				DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.304"),
968
		},
969
	},
970
	{
971
		.matches = {
972
				DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
973
				DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.305"),
974
		},
975
	},
976
	{
977
		.matches = {
978
				DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
979
				DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.306"),
980
		},
981
	},
982
	{
983
		.matches = {
984
				DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
985
				DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.307"),
986
		},
987
	},
988
	{}
989
};
990

991
static void asus_disable_nvme_d3cold(struct pci_dev *pdev)
992
{
993
	if (dmi_check_system(asus_nvme_broken_d3cold_table) > 0)
994
		pci_d3cold_disable(pdev);
995
}
996
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x9a09, asus_disable_nvme_d3cold);
997

998
#ifdef CONFIG_SUSPEND
999
/*
1000
 * Root Ports on some AMD SoCs advertise PME_Support for D3hot and D3cold, but
1001
 * if the SoC is put into a hardware sleep state by the amd-pmc driver, the
1002
 * Root Ports don't generate wakeup interrupts for USB devices.
1003
 *
1004
 * When suspending, remove D3hot and D3cold from the PME_Support advertised
1005
 * by the Root Port so we don't use those states if we're expecting wakeup
1006
 * interrupts.  Restore the advertised PME_Support when resuming.
1007
 */
1008
static void amd_rp_pme_suspend(struct pci_dev *dev)
1009
{
1010
	struct pci_dev *rp;
1011

1012
	/*
1013
	 * If system suspend is not in progress, we're doing runtime suspend, so
1014
	 * amd-pmc will not be involved so PMEs during D3 work as advertised.
1015
	 *
1016
	 * The PMEs *do* work if amd-pmc doesn't put the SoC in the hardware
1017
	 * sleep state, but we assume amd-pmc is always present.
1018
	 */
1019
	if (!pm_suspend_in_progress())
1020
		return;
1021

1022
	rp = pcie_find_root_port(dev);
1023
	if (!rp || !rp->pm_cap)
1024
		return;
1025

1026
	rp->pme_support &= ~((PCI_PM_CAP_PME_D3hot|PCI_PM_CAP_PME_D3cold) >>
1027
				    PCI_PM_CAP_PME_SHIFT);
1028
	dev_info_once(&rp->dev, "quirk: disabling D3cold for suspend\n");
1029
}
1030

1031
static void amd_rp_pme_resume(struct pci_dev *dev)
1032
{
1033
	struct pci_dev *rp;
1034
	u16 pmc;
1035

1036
	rp = pcie_find_root_port(dev);
1037
	if (!rp || !rp->pm_cap)
1038
		return;
1039

1040
	pci_read_config_word(rp, rp->pm_cap + PCI_PM_PMC, &pmc);
1041
	rp->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc);
1042
}
1043
/* Rembrandt (yellow_carp) */
1044
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x162e, amd_rp_pme_suspend);
1045
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x162e, amd_rp_pme_resume);
1046
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x162f, amd_rp_pme_suspend);
1047
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x162f, amd_rp_pme_resume);
1048
/* Phoenix (pink_sardine) */
1049
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x1668, amd_rp_pme_suspend);
1050
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1668, amd_rp_pme_resume);
1051
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x1669, amd_rp_pme_suspend);
1052
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1669, amd_rp_pme_resume);
1053

1054
/*
1055
 * Putting PCIe root ports on Ryzen SoCs with USB4 controllers into D3hot
1056
 * may cause problems when the system attempts wake up from s2idle.
1057
 *
1058
 * On the TUXEDO Sirius 16 Gen 1 with a specific old BIOS this manifests as
1059
 * a system hang.
1060
 */
1061
static const struct dmi_system_id quirk_tuxeo_rp_d3_dmi_table[] = {
1062
	{
1063
		.matches = {
1064
			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
1065
			DMI_EXACT_MATCH(DMI_BOARD_NAME, "APX958"),
1066
			DMI_EXACT_MATCH(DMI_BIOS_VERSION, "V1.00A00_20240108"),
1067
		},
1068
	},
1069
	{}
1070
};
1071

1072
static void quirk_tuxeo_rp_d3(struct pci_dev *pdev)
1073
{
1074
	struct pci_dev *root_pdev;
1075

1076
	if (dmi_check_system(quirk_tuxeo_rp_d3_dmi_table)) {
1077
		root_pdev = pcie_find_root_port(pdev);
1078
		if (root_pdev)
1079
			root_pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1080
	}
1081
}
1082
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1502, quirk_tuxeo_rp_d3);
1083
#endif /* CONFIG_SUSPEND */
1084

1085