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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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 *
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 */
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#ifndef _MHI_INT_H
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#define _MHI_INT_H
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#include "../common.h"
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extern const struct bus_type mhi_bus_type;
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/* Host request register */
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#define MHI_SOC_RESET_REQ_OFFSET			0xb0
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#define MHI_SOC_RESET_REQ				BIT(0)
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struct mhi_ctxt {
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	struct mhi_event_ctxt *er_ctxt;
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	struct mhi_chan_ctxt *chan_ctxt;
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	struct mhi_cmd_ctxt *cmd_ctxt;
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	dma_addr_t er_ctxt_addr;
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	dma_addr_t chan_ctxt_addr;
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	dma_addr_t cmd_ctxt_addr;
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};
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struct bhi_vec_entry {
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	__le64 dma_addr;
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	__le64 size;
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};
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enum mhi_fw_load_type {
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	MHI_FW_LOAD_BHI,	/* BHI only in PBL */
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	MHI_FW_LOAD_BHIE,	/* BHIe only in PBL */
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	MHI_FW_LOAD_FBC,	/* BHI in PBL followed by BHIe in SBL */
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	MHI_FW_LOAD_MAX,
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};
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enum mhi_ch_state_type {
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	MHI_CH_STATE_TYPE_RESET,
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	MHI_CH_STATE_TYPE_STOP,
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	MHI_CH_STATE_TYPE_START,
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	MHI_CH_STATE_TYPE_MAX,
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};
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#define MHI_CH_STATE_TYPE_LIST				\
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	ch_state_type(RESET,		"RESET")	\
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	ch_state_type(STOP,		"STOP")		\
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	ch_state_type_end(START,	"START")
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extern const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX];
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#define TO_CH_STATE_TYPE_STR(state) (((state) >= MHI_CH_STATE_TYPE_MAX) ? \
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				     "INVALID_STATE" : \
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				     mhi_ch_state_type_str[(state)])
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#define MHI_INVALID_BRSTMODE(mode) (mode != MHI_DB_BRST_DISABLE && \
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				    mode != MHI_DB_BRST_ENABLE)
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#define MHI_EE_LIST						\
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	mhi_ee(PBL,			"PRIMARY BOOTLOADER")	\
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	mhi_ee(SBL,			"SECONDARY BOOTLOADER")	\
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	mhi_ee(AMSS,			"MISSION MODE")		\
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	mhi_ee(RDDM,			"RAMDUMP DOWNLOAD MODE")\
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	mhi_ee(WFW,			"WLAN FIRMWARE")	\
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	mhi_ee(PTHRU,			"PASS THROUGH")		\
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	mhi_ee(EDL,			"EMERGENCY DOWNLOAD")	\
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	mhi_ee(FP,			"FLASH PROGRAMMER")	\
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	mhi_ee(DISABLE_TRANSITION,	"DISABLE")		\
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	mhi_ee_end(NOT_SUPPORTED,	"NOT SUPPORTED")
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extern const char * const mhi_ee_str[MHI_EE_MAX];
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#define TO_MHI_EXEC_STR(ee) (((ee) >= MHI_EE_MAX) ? \
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			     "INVALID_EE" : mhi_ee_str[ee])
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#define MHI_IN_PBL(ee) (ee == MHI_EE_PBL || ee == MHI_EE_PTHRU || \
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			ee == MHI_EE_EDL)
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#define MHI_POWER_UP_CAPABLE(ee) (MHI_IN_PBL(ee) || ee == MHI_EE_AMSS)
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#define MHI_FW_LOAD_CAPABLE(ee) (ee == MHI_EE_PBL || ee == MHI_EE_EDL)
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#define MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || ee == MHI_EE_WFW || \
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				 ee == MHI_EE_FP)
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enum dev_st_transition {
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	DEV_ST_TRANSITION_PBL,
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	DEV_ST_TRANSITION_READY,
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	DEV_ST_TRANSITION_SBL,
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	DEV_ST_TRANSITION_MISSION_MODE,
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	DEV_ST_TRANSITION_FP,
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	DEV_ST_TRANSITION_SYS_ERR,
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	DEV_ST_TRANSITION_DISABLE,
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	DEV_ST_TRANSITION_DISABLE_DESTROY_DEVICE,
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	DEV_ST_TRANSITION_MAX,
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};
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#define DEV_ST_TRANSITION_LIST					\
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	dev_st_trans(PBL,		"PBL")			\
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	dev_st_trans(READY,		"READY")		\
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	dev_st_trans(SBL,		"SBL")			\
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	dev_st_trans(MISSION_MODE,	"MISSION MODE")		\
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	dev_st_trans(FP,		"FLASH PROGRAMMER")	\
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	dev_st_trans(SYS_ERR,		"SYS ERROR")		\
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	dev_st_trans(DISABLE,		"DISABLE")		\
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	dev_st_trans_end(DISABLE_DESTROY_DEVICE, "DISABLE (DESTROY DEVICE)")
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extern const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX];
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#define TO_DEV_STATE_TRANS_STR(state) (((state) >= DEV_ST_TRANSITION_MAX) ? \
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				"INVALID_STATE" : dev_state_tran_str[state])
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/* internal power states */
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enum mhi_pm_state {
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	MHI_PM_STATE_DISABLE,
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	MHI_PM_STATE_POR,
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	MHI_PM_STATE_M0,
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	MHI_PM_STATE_M2,
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	MHI_PM_STATE_M3_ENTER,
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	MHI_PM_STATE_M3,
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	MHI_PM_STATE_M3_EXIT,
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	MHI_PM_STATE_FW_DL_ERR,
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	MHI_PM_STATE_SYS_ERR_DETECT,
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	MHI_PM_STATE_SYS_ERR_PROCESS,
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	MHI_PM_STATE_SYS_ERR_FAIL,
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	MHI_PM_STATE_SHUTDOWN_PROCESS,
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	MHI_PM_STATE_LD_ERR_FATAL_DETECT,
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	MHI_PM_STATE_MAX
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};
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#define MHI_PM_STATE_LIST							\
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	mhi_pm_state(DISABLE,			"DISABLE")			\
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	mhi_pm_state(POR,			"POWER ON RESET")		\
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	mhi_pm_state(M0,			"M0")				\
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	mhi_pm_state(M2,			"M2")				\
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	mhi_pm_state(M3_ENTER,			"M?->M3")			\
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	mhi_pm_state(M3,			"M3")				\
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	mhi_pm_state(M3_EXIT,			"M3->M0")			\
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	mhi_pm_state(FW_DL_ERR,			"Firmware Download Error")	\
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	mhi_pm_state(SYS_ERR_DETECT,		"SYS ERROR Detect")		\
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	mhi_pm_state(SYS_ERR_PROCESS,		"SYS ERROR Process")		\
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	mhi_pm_state(SYS_ERR_FAIL,		"SYS ERROR Failure")		\
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	mhi_pm_state(SHUTDOWN_PROCESS,		"SHUTDOWN Process")		\
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	mhi_pm_state_end(LD_ERR_FATAL_DETECT,	"Linkdown or Error Fatal Detect")
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#define MHI_PM_DISABLE					BIT(0)
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#define MHI_PM_POR					BIT(1)
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#define MHI_PM_M0					BIT(2)
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#define MHI_PM_M2					BIT(3)
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#define MHI_PM_M3_ENTER					BIT(4)
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#define MHI_PM_M3					BIT(5)
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#define MHI_PM_M3_EXIT					BIT(6)
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/* firmware download failure state */
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#define MHI_PM_FW_DL_ERR				BIT(7)
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#define MHI_PM_SYS_ERR_DETECT				BIT(8)
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#define MHI_PM_SYS_ERR_PROCESS				BIT(9)
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#define MHI_PM_SYS_ERR_FAIL				BIT(10)
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#define MHI_PM_SHUTDOWN_PROCESS				BIT(11)
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/* link not accessible */
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#define MHI_PM_LD_ERR_FATAL_DETECT			BIT(12)
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#define MHI_REG_ACCESS_VALID(pm_state)			((pm_state & (MHI_PM_POR | MHI_PM_M0 | \
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						MHI_PM_M2 | MHI_PM_M3_ENTER | MHI_PM_M3_EXIT | \
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						MHI_PM_SYS_ERR_DETECT | MHI_PM_SYS_ERR_PROCESS | \
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						MHI_PM_SYS_ERR_FAIL | MHI_PM_SHUTDOWN_PROCESS |  \
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						MHI_PM_FW_DL_ERR)))
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#define MHI_PM_IN_ERROR_STATE(pm_state)			(pm_state >= MHI_PM_FW_DL_ERR)
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#define MHI_PM_IN_FATAL_STATE(pm_state)			(pm_state == MHI_PM_LD_ERR_FATAL_DETECT)
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#define MHI_DB_ACCESS_VALID(mhi_cntrl)			(mhi_cntrl->pm_state & mhi_cntrl->db_access)
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#define MHI_WAKE_DB_CLEAR_VALID(pm_state)		(pm_state & (MHI_PM_M0 | \
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							MHI_PM_M2 | MHI_PM_M3_EXIT))
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#define MHI_WAKE_DB_SET_VALID(pm_state)			(pm_state & MHI_PM_M2)
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#define MHI_WAKE_DB_FORCE_SET_VALID(pm_state)		MHI_WAKE_DB_CLEAR_VALID(pm_state)
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#define MHI_EVENT_ACCESS_INVALID(pm_state)		(pm_state == MHI_PM_DISABLE || \
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							MHI_PM_IN_ERROR_STATE(pm_state))
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#define MHI_PM_IN_SUSPEND_STATE(pm_state)		(pm_state & \
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							(MHI_PM_M3_ENTER | MHI_PM_M3))
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#define MHI_PM_FATAL_ERROR(pm_state)			((pm_state == MHI_PM_FW_DL_ERR) || \
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							(pm_state >= MHI_PM_SYS_ERR_FAIL))
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#define NR_OF_CMD_RINGS					1
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#define CMD_EL_PER_RING					128
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#define PRIMARY_CMD_RING				0
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#define MHI_DEV_WAKE_DB					127
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#define MHI_MAX_MTU					0xffff
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#define MHI_RANDOM_U32_NONZERO(bmsk)			(get_random_u32_inclusive(1, bmsk))
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enum mhi_er_type {
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	MHI_ER_TYPE_INVALID = 0x0,
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	MHI_ER_TYPE_VALID = 0x1,
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};
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struct db_cfg {
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	bool reset_req;
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	bool db_mode;
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	u32 pollcfg;
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	enum mhi_db_brst_mode brstmode;
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	dma_addr_t db_val;
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	void (*process_db)(struct mhi_controller *mhi_cntrl,
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			   struct db_cfg *db_cfg, void __iomem *io_addr,
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			   dma_addr_t db_val);
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};
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struct mhi_pm_transitions {
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	enum mhi_pm_state from_state;
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	u32 to_states;
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};
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struct state_transition {
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	struct list_head node;
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	enum dev_st_transition state;
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};
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struct mhi_ring {
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	dma_addr_t dma_handle;
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	dma_addr_t iommu_base;
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	__le64 *ctxt_wp; /* point to ctxt wp */
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	void *pre_aligned;
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	void *base;
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	void *rp;
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	void *wp;
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	size_t el_size;
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	size_t len;
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	size_t elements;
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	size_t alloc_size;
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	void __iomem *db_addr;
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};
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struct mhi_cmd {
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	struct mhi_ring ring;
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	spinlock_t lock;
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};
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struct mhi_buf_info {
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	void *v_addr;
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	void *bb_addr;
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	void *wp;
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	void *cb_buf;
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	dma_addr_t p_addr;
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	size_t len;
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	enum dma_data_direction dir;
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	bool used; /* Indicates whether the buffer is used or not */
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	bool pre_mapped; /* Already pre-mapped by client */
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};
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struct mhi_event {
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	struct mhi_controller *mhi_cntrl;
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	struct mhi_chan *mhi_chan; /* dedicated to channel */
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	u32 er_index;
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	u32 intmod;
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	u32 irq;
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	int chan; /* this event ring is dedicated to a channel (optional) */
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	u32 priority;
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	enum mhi_er_data_type data_type;
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	struct mhi_ring ring;
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	struct db_cfg db_cfg;
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	struct tasklet_struct task;
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	spinlock_t lock;
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	int (*process_event)(struct mhi_controller *mhi_cntrl,
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			     struct mhi_event *mhi_event,
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			     u32 event_quota);
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	bool hw_ring;
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	bool cl_manage;
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	bool offload_ev; /* managed by a device driver */
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};
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struct mhi_chan {
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	const char *name;
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	/*
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	 * Important: When consuming, increment tre_ring first and when
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	 * releasing, decrement buf_ring first. If tre_ring has space, buf_ring
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	 * is guaranteed to have space so we do not need to check both rings.
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	 */
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	struct mhi_ring buf_ring;
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	struct mhi_ring tre_ring;
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	u32 chan;
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	u32 er_index;
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	u32 intmod;
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	enum mhi_ch_type type;
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	enum dma_data_direction dir;
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	struct db_cfg db_cfg;
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	enum mhi_ch_ee_mask ee_mask;
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	enum mhi_ch_state ch_state;
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	enum mhi_ev_ccs ccs;
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	struct mhi_device *mhi_dev;
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	void (*xfer_cb)(struct mhi_device *mhi_dev, struct mhi_result *result);
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	struct mutex mutex;
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	struct completion completion;
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	rwlock_t lock;
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	struct list_head node;
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	bool lpm_notify;
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	bool configured;
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	bool offload_ch;
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	bool pre_alloc;
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	bool wake_capable;
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};
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/* Default MHI timeout */
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#define MHI_TIMEOUT_MS (1000)
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/* debugfs related functions */
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#ifdef CONFIG_MHI_BUS_DEBUG
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void mhi_create_debugfs(struct mhi_controller *mhi_cntrl);
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void mhi_destroy_debugfs(struct mhi_controller *mhi_cntrl);
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void mhi_debugfs_init(void);
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void mhi_debugfs_exit(void);
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#else
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static inline void mhi_create_debugfs(struct mhi_controller *mhi_cntrl)
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{
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}
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static inline void mhi_destroy_debugfs(struct mhi_controller *mhi_cntrl)
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{
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}
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static inline void mhi_debugfs_init(void)
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{
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}
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static inline void mhi_debugfs_exit(void)
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{
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}
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#endif
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struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl);
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int mhi_destroy_device(struct device *dev, void *data);
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void mhi_create_devices(struct mhi_controller *mhi_cntrl);
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int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
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			 struct image_info **image_info, size_t alloc_size);
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void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl,
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			 struct image_info *image_info);
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/* Power management APIs */
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enum mhi_pm_state __must_check mhi_tryset_pm_state(
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					struct mhi_controller *mhi_cntrl,
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					enum mhi_pm_state state);
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const char *to_mhi_pm_state_str(u32 state);
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int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
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			       enum dev_st_transition state);
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void mhi_pm_st_worker(struct work_struct *work);
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void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl);
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int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl);
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int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl);
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void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl);
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int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl);
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int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl);
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int mhi_send_cmd(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,
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		 enum mhi_cmd_type cmd);
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int mhi_download_amss_image(struct mhi_controller *mhi_cntrl);
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static inline bool mhi_is_active(struct mhi_controller *mhi_cntrl)
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{
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	return (mhi_cntrl->dev_state >= MHI_STATE_M0 &&
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		mhi_cntrl->dev_state <= MHI_STATE_M3_FAST);
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}
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static inline void mhi_trigger_resume(struct mhi_controller *mhi_cntrl)
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{
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	pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0);
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	mhi_cntrl->runtime_get(mhi_cntrl);
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	mhi_cntrl->runtime_put(mhi_cntrl);
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}
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/* Register access methods */
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void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, struct db_cfg *db_cfg,
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		     void __iomem *db_addr, dma_addr_t db_val);
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void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl,
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			     struct db_cfg *db_mode, void __iomem *db_addr,
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			     dma_addr_t db_val);
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int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
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			      void __iomem *base, u32 offset, u32 *out);
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int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,
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				    void __iomem *base, u32 offset, u32 mask,
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				    u32 *out);
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int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
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				    void __iomem *base, u32 offset, u32 mask,
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				    u32 val, u32 delayus, u32 timeout_ms);
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void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
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		   u32 offset, u32 val);
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int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl,
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				     void __iomem *base, u32 offset, u32 mask,
378
				     u32 val);
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void mhi_ring_er_db(struct mhi_event *mhi_event);
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void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr,
381
		  dma_addr_t db_val);
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void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd);
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void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
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		      struct mhi_chan *mhi_chan);
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/* Initialization methods */
387
int mhi_init_mmio(struct mhi_controller *mhi_cntrl);
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int mhi_rddm_prepare(struct mhi_controller *mhi_cntrl,
389
		      struct image_info *img_info);
390
void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl);
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392
/* Automatically allocate and queue inbound buffers */
393
#define MHI_CH_INBOUND_ALLOC_BUFS BIT(0)
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int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
395
		       struct mhi_chan *mhi_chan);
396
void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
397
			  struct mhi_chan *mhi_chan);
398
void mhi_reset_chan(struct mhi_controller *mhi_cntrl,
399
		    struct mhi_chan *mhi_chan);
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/* Event processing methods */
402
void mhi_ctrl_ev_task(unsigned long data);
403
void mhi_ev_task(unsigned long data);
404
int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl,
405
				struct mhi_event *mhi_event, u32 event_quota);
406
int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl,
407
			     struct mhi_event *mhi_event, u32 event_quota);
408
void mhi_uevent_notify(struct mhi_controller *mhi_cntrl, enum mhi_ee_type ee);
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/* ISR handlers */
411
irqreturn_t mhi_irq_handler(int irq_number, void *dev);
412
irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev);
413
irqreturn_t mhi_intvec_handler(int irq_number, void *dev);
414

415
int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,
416
		struct mhi_buf_info *info, enum mhi_flags flags);
417
int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl,
418
			 struct mhi_buf_info *buf_info);
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int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl,
420
			  struct mhi_buf_info *buf_info);
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void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl,
422
			    struct mhi_buf_info *buf_info);
423
void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl,
424
			     struct mhi_buf_info *buf_info);
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#endif /* _MHI_INT_H */
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