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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2024 HiSilicon Limited. */
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/uacce.h>
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#include "zip.h"
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/* memory */
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#define DAE_MEM_START_OFFSET		0x331040
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#define DAE_MEM_DONE_OFFSET		0x331044
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#define DAE_MEM_START_MASK		0x1
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#define DAE_MEM_DONE_MASK		0x1
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#define DAE_REG_RD_INTVRL_US		10
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#define DAE_REG_RD_TMOUT_US		USEC_PER_SEC
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#define DAE_ALG_NAME			"hashagg"
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#define DAE_V5_ALG_NAME			"hashagg\nudma\nhashjoin\ngather"
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/* error */
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#define DAE_AXI_CFG_OFFSET		0x331000
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#define DAE_AXI_SHUTDOWN_MASK		(BIT(0) | BIT(5))
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#define DAE_ERR_SOURCE_OFFSET		0x331C84
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#define DAE_ERR_STATUS_OFFSET		0x331C88
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#define DAE_ERR_CE_OFFSET		0x331CA0
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#define DAE_ERR_CE_MASK			BIT(3)
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#define DAE_ERR_NFE_OFFSET		0x331CA4
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#define DAE_ERR_NFE_MASK		0x17
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#define DAE_ERR_FE_OFFSET		0x331CA8
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#define DAE_ERR_FE_MASK			0
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#define DAE_ECC_MBIT_MASK		BIT(2)
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#define DAE_ECC_INFO_OFFSET		0x33400C
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#define DAE_ERR_SHUTDOWN_OFFSET		0x331CAC
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#define DAE_ERR_SHUTDOWN_MASK		0x17
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#define DAE_ERR_ENABLE_OFFSET		0x331C80
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#define DAE_ERR_ENABLE_MASK		(DAE_ERR_FE_MASK | DAE_ERR_NFE_MASK | DAE_ERR_CE_MASK)
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#define DAE_AM_CTRL_GLOBAL_OFFSET	0x330000
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#define DAE_AM_RETURN_OFFSET		0x330150
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#define DAE_AM_RETURN_MASK		0x3
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#define DAE_AXI_CFG_OFFSET		0x331000
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#define DAE_AXI_SHUTDOWN_EN_MASK	(BIT(0) | BIT(5))
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struct hisi_dae_hw_error {
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	u32 int_msk;
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	const char *msg;
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};
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static const struct hisi_dae_hw_error dae_hw_error[] = {
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	{ .int_msk = BIT(0), .msg = "dae_axi_bus_err" },
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	{ .int_msk = BIT(1), .msg = "dae_axi_poison_err" },
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	{ .int_msk = BIT(2), .msg = "dae_ecc_2bit_err" },
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	{ .int_msk = BIT(3), .msg = "dae_ecc_1bit_err" },
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	{ .int_msk = BIT(4), .msg = "dae_fsm_hbeat_err" },
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};
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static inline bool dae_is_support(struct hisi_qm *qm)
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{
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	if (test_bit(QM_SUPPORT_DAE, &qm->caps))
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		return true;
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	return false;
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}
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int hisi_dae_set_user_domain(struct hisi_qm *qm)
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{
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	u32 val;
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	int ret;
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	if (!dae_is_support(qm))
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		return 0;
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	val = readl(qm->io_base + DAE_MEM_START_OFFSET);
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	val |= DAE_MEM_START_MASK;
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	writel(val, qm->io_base + DAE_MEM_START_OFFSET);
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	ret = readl_relaxed_poll_timeout(qm->io_base + DAE_MEM_DONE_OFFSET, val,
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					 val & DAE_MEM_DONE_MASK,
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					 DAE_REG_RD_INTVRL_US, DAE_REG_RD_TMOUT_US);
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	if (ret)
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		pci_err(qm->pdev, "failed to init dae memory!\n");
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	return ret;
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}
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int hisi_dae_set_alg(struct hisi_qm *qm)
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{
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	const char *alg_name;
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	size_t len;
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	if (!dae_is_support(qm))
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		return 0;
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	if (!qm->uacce)
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		return 0;
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	if (qm->ver >= QM_HW_V5)
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		alg_name = DAE_V5_ALG_NAME;
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	else
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		alg_name = DAE_ALG_NAME;
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	len = strlen(qm->uacce->algs);
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	/* A line break may be required */
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	if (len + strlen(alg_name) + 1 >= QM_DEV_ALG_MAX_LEN) {
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		pci_err(qm->pdev, "algorithm name is too long!\n");
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		return -EINVAL;
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	}
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	if (len)
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		strcat((char *)qm->uacce->algs, "\n");
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	strcat((char *)qm->uacce->algs, alg_name);
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	return 0;
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}
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static void hisi_dae_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
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{
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	u32 axi_val, err_val;
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	axi_val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);
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	if (enable) {
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		axi_val |= DAE_AXI_SHUTDOWN_MASK;
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		err_val = DAE_ERR_SHUTDOWN_MASK;
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	} else {
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		axi_val &= ~DAE_AXI_SHUTDOWN_MASK;
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		err_val = 0;
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	}
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	writel(axi_val, qm->io_base + DAE_AXI_CFG_OFFSET);
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	writel(err_val, qm->io_base + DAE_ERR_SHUTDOWN_OFFSET);
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}
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void hisi_dae_hw_error_enable(struct hisi_qm *qm)
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{
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	if (!dae_is_support(qm))
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		return;
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	/* clear dae hw error source if having */
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	writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_SOURCE_OFFSET);
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	/* configure error type */
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	writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);
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	writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);
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	writel(DAE_ERR_FE_MASK, qm->io_base + DAE_ERR_FE_OFFSET);
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	hisi_dae_master_ooo_ctrl(qm, true);
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	/* enable dae hw error interrupts */
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	writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_ENABLE_OFFSET);
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}
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void hisi_dae_hw_error_disable(struct hisi_qm *qm)
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{
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	if (!dae_is_support(qm))
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		return;
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	writel(0, qm->io_base + DAE_ERR_ENABLE_OFFSET);
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	hisi_dae_master_ooo_ctrl(qm, false);
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}
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static u32 hisi_dae_get_hw_err_status(struct hisi_qm *qm)
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{
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	return readl(qm->io_base + DAE_ERR_STATUS_OFFSET);
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}
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static void hisi_dae_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
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{
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	if (!dae_is_support(qm))
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		return;
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	writel(err_sts, qm->io_base + DAE_ERR_SOURCE_OFFSET);
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}
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static void hisi_dae_disable_error_report(struct hisi_qm *qm, u32 err_type)
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{
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	writel(DAE_ERR_NFE_MASK & (~err_type), qm->io_base + DAE_ERR_NFE_OFFSET);
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}
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static void hisi_dae_enable_error_report(struct hisi_qm *qm)
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{
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	writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);
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	writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);
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}
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static void hisi_dae_log_hw_error(struct hisi_qm *qm, u32 err_type)
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{
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	const struct hisi_dae_hw_error *err = dae_hw_error;
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	struct device *dev = &qm->pdev->dev;
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	u32 ecc_info;
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	size_t i;
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	for (i = 0; i < ARRAY_SIZE(dae_hw_error); i++) {
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		err = &dae_hw_error[i];
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		if (!(err->int_msk & err_type))
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			continue;
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		dev_err(dev, "%s [error status=0x%x] found\n",
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			err->msg, err->int_msk);
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		if (err->int_msk & DAE_ECC_MBIT_MASK) {
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			ecc_info = readl(qm->io_base + DAE_ECC_INFO_OFFSET);
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			dev_err(dev, "dae multi ecc sram info 0x%x\n", ecc_info);
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		}
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	}
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}
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enum acc_err_result hisi_dae_get_err_result(struct hisi_qm *qm)
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{
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	u32 err_status;
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	if (!dae_is_support(qm))
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		return ACC_ERR_NONE;
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	err_status = hisi_dae_get_hw_err_status(qm);
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	if (!err_status)
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		return ACC_ERR_NONE;
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	hisi_dae_log_hw_error(qm, err_status);
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	if (err_status & DAE_ERR_NFE_MASK) {
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		/* Disable the same error reporting until device is recovered. */
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		hisi_dae_disable_error_report(qm, err_status);
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		return ACC_ERR_NEED_RESET;
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	}
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	hisi_dae_clear_hw_err_status(qm, err_status);
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	/* Avoid firmware disable error report, re-enable. */
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	hisi_dae_enable_error_report(qm);
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	return ACC_ERR_RECOVERED;
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}
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bool hisi_dae_dev_is_abnormal(struct hisi_qm *qm)
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{
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	u32 err_status;
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	if (!dae_is_support(qm))
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		return false;
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	err_status = hisi_dae_get_hw_err_status(qm);
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	if (err_status & DAE_ERR_NFE_MASK)
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		return true;
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	return false;
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}
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int hisi_dae_close_axi_master_ooo(struct hisi_qm *qm)
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{
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	u32 val;
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	int ret;
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	if (!dae_is_support(qm))
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		return 0;
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	val = readl(qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);
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	val |= BIT(0);
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	writel(val, qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);
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	ret = readl_relaxed_poll_timeout(qm->io_base + DAE_AM_RETURN_OFFSET,
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					 val, (val == DAE_AM_RETURN_MASK),
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					 DAE_REG_RD_INTVRL_US, DAE_REG_RD_TMOUT_US);
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	if (ret)
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		dev_err(&qm->pdev->dev, "failed to close dae axi ooo!\n");
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	return ret;
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}
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void hisi_dae_open_axi_master_ooo(struct hisi_qm *qm)
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{
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	u32 val;
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	if (!dae_is_support(qm))
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		return;
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	val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);
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	writel(val & ~DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);
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	writel(val | DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);
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}
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