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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
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 */
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#ifndef IOATDMA_H
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#define IOATDMA_H
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/dmapool.h>
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#include <linux/cache.h>
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#include <linux/pci_ids.h>
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#include <linux/circ_buf.h>
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#include <linux/interrupt.h>
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#include "registers.h"
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#include "hw.h"
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#define IOAT_DMA_VERSION  "5.00"
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#define IOAT_DMA_DCA_ANY_CPU		~0
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int system_has_dca_enabled(struct pci_dev *pdev);
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#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev)
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#define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev)
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#define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev)
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#define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80)
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/* ioat hardware assumes at least two sources for raid operations */
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#define src_cnt_to_sw(x) ((x) + 2)
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#define src_cnt_to_hw(x) ((x) - 2)
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#define ndest_to_sw(x) ((x) + 1)
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#define ndest_to_hw(x) ((x) - 1)
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#define src16_cnt_to_sw(x) ((x) + 9)
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#define src16_cnt_to_hw(x) ((x) - 9)
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/*
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 * workaround for IOAT ver.3.0 null descriptor issue
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 * (channel returns error when size is 0)
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 */
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#define NULL_DESC_BUFFER_SIZE 1
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enum ioat_irq_mode {
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	IOAT_NOIRQ = 0,
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	IOAT_MSIX,
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	IOAT_MSI,
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	IOAT_INTX
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};
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/**
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 * struct ioatdma_device - internal representation of a IOAT device
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 * @pdev: PCI-Express device
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 * @reg_base: MMIO register space base address
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 * @completion_pool: DMA buffers for completion ops
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 * @sed_hw_pool: DMA super descriptor pools
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 * @dma_dev: embedded struct dma_device
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 * @version: version of ioatdma device
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 * @msix_entries: irq handlers
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 * @idx: per channel data
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 * @dca: direct cache access context
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 * @irq_mode: interrupt mode (INTX, MSI, MSIX)
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 * @cap: read DMA capabilities register
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 */
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struct ioatdma_device {
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	struct pci_dev *pdev;
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	void __iomem *reg_base;
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	struct dma_pool *completion_pool;
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#define MAX_SED_POOLS	5
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	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
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	struct dma_device dma_dev;
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	u8 version;
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#define IOAT_MAX_CHANS 4
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	struct msix_entry msix_entries[IOAT_MAX_CHANS];
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	struct ioatdma_chan *idx[IOAT_MAX_CHANS];
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	struct dca_provider *dca;
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	enum ioat_irq_mode irq_mode;
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	u32 cap;
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	int chancnt;
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	/* shadow version for CB3.3 chan reset errata workaround */
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	u64 msixtba0;
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	u64 msixdata0;
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	u32 msixpba;
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};
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#define IOAT_MAX_ORDER 16
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#define IOAT_MAX_DESCS (1 << IOAT_MAX_ORDER)
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#define IOAT_CHUNK_SIZE (SZ_512K)
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#define IOAT_DESCS_PER_CHUNK (IOAT_CHUNK_SIZE / IOAT_DESC_SZ)
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struct ioat_descs {
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	void *virt;
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	dma_addr_t hw;
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};
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struct ioatdma_chan {
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	struct dma_chan dma_chan;
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	void __iomem *reg_base;
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	dma_addr_t last_completion;
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	spinlock_t cleanup_lock;
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	unsigned long state;
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	#define IOAT_CHAN_DOWN 0
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	#define IOAT_COMPLETION_ACK 1
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	#define IOAT_RESET_PENDING 2
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	#define IOAT_KOBJ_INIT_FAIL 3
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	#define IOAT_RUN 5
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	#define IOAT_CHAN_ACTIVE 6
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	struct timer_list timer;
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	#define RESET_DELAY msecs_to_jiffies(100)
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	struct ioatdma_device *ioat_dma;
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	dma_addr_t completion_dma;
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	u64 *completion;
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	struct tasklet_struct cleanup_task;
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	struct kobject kobj;
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/* ioat v2 / v3 channel attributes
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 * @xfercap_log; log2 of channel max transfer length (for fast division)
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 * @head: allocated index
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 * @issued: hardware notification point
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 * @tail: cleanup index
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 * @dmacount: identical to 'head' except for occasionally resetting to zero
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 * @alloc_order: log2 of the number of allocated descriptors
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 * @produce: number of descriptors to produce at submit time
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 * @ring: software ring buffer implementation of hardware ring
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 * @prep_lock: serializes descriptor preparation (producers)
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 */
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	size_t xfercap_log;
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	u16 head;
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	u16 issued;
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	u16 tail;
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	u16 dmacount;
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	u16 alloc_order;
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	u16 produce;
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	struct ioat_ring_ent **ring;
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	spinlock_t prep_lock;
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	struct ioat_descs descs[IOAT_MAX_DESCS / IOAT_DESCS_PER_CHUNK];
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	int desc_chunks;
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	int intr_coalesce;
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	int prev_intr_coalesce;
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};
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struct ioat_sysfs_entry {
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	struct attribute attr;
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	ssize_t (*show)(struct dma_chan *, char *);
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	ssize_t (*store)(struct dma_chan *, const char *, size_t);
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};
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/**
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 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
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 * @hw: hardware SED
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 * @dma: dma address for the SED
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 * @parent: point to the dma descriptor that's the parent
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 * @hw_pool: descriptor pool index
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 */
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struct ioat_sed_ent {
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	struct ioat_sed_raw_descriptor *hw;
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	dma_addr_t dma;
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	struct ioat_ring_ent *parent;
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	unsigned int hw_pool;
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};
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/**
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 * struct ioat_ring_ent - wrapper around hardware descriptor
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 * @hw: hardware DMA descriptor (for memcpy)
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 * @xor: hardware xor descriptor
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 * @xor_ex: hardware xor extension descriptor
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 * @pq: hardware pq descriptor
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 * @pq_ex: hardware pq extension descriptor
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 * @pqu: hardware pq update descriptor
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 * @raw: hardware raw (un-typed) descriptor
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 * @txd: the generic software descriptor for all engines
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 * @len: total transaction length for unmap
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 * @result: asynchronous result of validate operations
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 * @id: identifier for debug
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 * @sed: pointer to super extended descriptor sw desc
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 */
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struct ioat_ring_ent {
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	union {
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		struct ioat_dma_descriptor *hw;
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		struct ioat_xor_descriptor *xor;
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		struct ioat_xor_ext_descriptor *xor_ex;
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		struct ioat_pq_descriptor *pq;
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		struct ioat_pq_ext_descriptor *pq_ex;
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		struct ioat_pq_update_descriptor *pqu;
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		struct ioat_raw_descriptor *raw;
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	};
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	size_t len;
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	struct dma_async_tx_descriptor txd;
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	enum sum_check_flags *result;
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	#ifdef DEBUG
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	int id;
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	#endif
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	struct ioat_sed_ent *sed;
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};
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extern const struct sysfs_ops ioat_sysfs_ops;
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extern struct ioat_sysfs_entry ioat_version_attr;
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extern struct ioat_sysfs_entry ioat_cap_attr;
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extern int ioat_pending_level;
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extern struct kobj_type ioat_ktype;
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extern struct kmem_cache *ioat_cache;
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extern struct kmem_cache *ioat_sed_cache;
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static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c)
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{
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	return container_of(c, struct ioatdma_chan, dma_chan);
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}
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/* wrapper around hardware descriptor format + additional software fields */
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#ifdef DEBUG
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#define set_desc_id(desc, i) ((desc)->id = (i))
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#define desc_id(desc) ((desc)->id)
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#else
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#define set_desc_id(desc, i)
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#define desc_id(desc) (0)
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#endif
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static inline void
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__dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw,
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		struct dma_async_tx_descriptor *tx, int id)
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{
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	struct device *dev = to_dev(ioat_chan);
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	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
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		" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
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		(unsigned long long) tx->phys,
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		(unsigned long long) hw->next, tx->cookie, tx->flags,
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		hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
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}
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#define dump_desc_dbg(c, d) \
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	({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; })
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static inline struct ioatdma_chan *
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ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
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{
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	return ioat_dma->idx[index];
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}
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static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
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{
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	return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
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}
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static inline u64 ioat_chansts_to_addr(u64 status)
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{
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	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
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}
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static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan)
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{
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	return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
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}
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static inline void ioat_suspend(struct ioatdma_chan *ioat_chan)
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{
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	u8 ver = ioat_chan->ioat_dma->version;
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	writeb(IOAT_CHANCMD_SUSPEND,
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	       ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
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}
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static inline void ioat_reset(struct ioatdma_chan *ioat_chan)
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{
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	u8 ver = ioat_chan->ioat_dma->version;
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	writeb(IOAT_CHANCMD_RESET,
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	       ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
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}
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static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan)
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{
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	u8 ver = ioat_chan->ioat_dma->version;
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	u8 cmd;
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	cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
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	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
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}
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static inline bool is_ioat_active(unsigned long status)
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{
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	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
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}
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static inline bool is_ioat_idle(unsigned long status)
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{
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	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
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}
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static inline bool is_ioat_halted(unsigned long status)
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{
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	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
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}
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static inline bool is_ioat_suspended(unsigned long status)
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{
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	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
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}
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/* channel was fatally programmed */
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static inline bool is_ioat_bug(unsigned long err)
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{
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	return !!err;
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}
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static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
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{
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	return 1 << ioat_chan->alloc_order;
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}
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/* count of descriptors in flight with the engine */
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static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)
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{
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	return CIRC_CNT(ioat_chan->head, ioat_chan->tail,
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			ioat_ring_size(ioat_chan));
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}
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/* count of descriptors pending submission to hardware */
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static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan)
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{
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	return CIRC_CNT(ioat_chan->head, ioat_chan->issued,
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			ioat_ring_size(ioat_chan));
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}
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static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan)
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{
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	return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan);
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}
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static inline u16
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ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len)
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{
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	u16 num_descs = len >> ioat_chan->xfercap_log;
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	num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1));
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	return num_descs;
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}
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static inline struct ioat_ring_ent *
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ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx)
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{
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	return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)];
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}
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static inline void
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ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr)
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{
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	writel(addr & 0x00000000FFFFFFFF,
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	       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
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	writel(addr >> 32,
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	       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
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}
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/* IOAT Prep functions */
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struct dma_async_tx_descriptor *
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ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
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			   dma_addr_t dma_src, size_t len, unsigned long flags);
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struct dma_async_tx_descriptor *
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ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags);
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struct dma_async_tx_descriptor *
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ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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	       unsigned int src_cnt, size_t len, unsigned long flags);
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struct dma_async_tx_descriptor *
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ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
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		    unsigned int src_cnt, size_t len,
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		    enum sum_check_flags *result, unsigned long flags);
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struct dma_async_tx_descriptor *
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ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
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	      unsigned int src_cnt, const unsigned char *scf, size_t len,
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	      unsigned long flags);
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struct dma_async_tx_descriptor *
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ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
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		  unsigned int src_cnt, const unsigned char *scf, size_t len,
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		  enum sum_check_flags *pqres, unsigned long flags);
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struct dma_async_tx_descriptor *
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ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
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		 unsigned int src_cnt, size_t len, unsigned long flags);
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struct dma_async_tx_descriptor *
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ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
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		     unsigned int src_cnt, size_t len,
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		     enum sum_check_flags *result, unsigned long flags);
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/* IOAT Operation functions */
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irqreturn_t ioat_dma_do_interrupt(int irq, void *data);
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irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data);
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struct ioat_ring_ent **
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ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags);
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void ioat_start_null_desc(struct ioatdma_chan *ioat_chan);
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void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan);
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int ioat_reset_hw(struct ioatdma_chan *ioat_chan);
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enum dma_status
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ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
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		struct dma_tx_state *txstate);
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void ioat_cleanup_event(struct tasklet_struct *t);
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void ioat_timer_event(struct timer_list *t);
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int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs);
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void ioat_issue_pending(struct dma_chan *chan);
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/* IOAT Init functions */
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bool is_bwd_ioat(struct pci_dev *pdev);
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struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type);
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void ioat_kobject_del(struct ioatdma_device *ioat_dma);
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int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma);
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void ioat_stop(struct ioatdma_chan *ioat_chan);
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#endif /* IOATDMA_H */
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