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// SPDX-License-Identifier: GPL-2.0
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//! GSP Sequencer implementation for Pre-hopper GSP boot sequence.
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use core::array;
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use kernel::{
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    device,
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    io::{
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        poll::read_poll_timeout,
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        Io, //
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    },
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    prelude::*,
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    sync::aref::ARef,
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    time::{
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        delay::fsleep,
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        Delta, //
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    },
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    transmute::FromBytes, //
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};
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use crate::{
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    driver::Bar0,
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    falcon::{
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        gsp::Gsp,
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        sec2::Sec2,
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        Falcon, //
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    },
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    gsp::{
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        cmdq::{
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            Cmdq,
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            MessageFromGsp, //
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        },
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        fw,
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    },
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    num::FromSafeCast,
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    sbuffer::SBufferIter,
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};
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/// GSP Sequencer information containing the command sequence and data.
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struct GspSequence {
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    /// Current command index for error reporting.
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    cmd_index: u32,
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    /// Command data buffer containing the sequence of commands.
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    cmd_data: KVec<u8>,
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}
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impl MessageFromGsp for GspSequence {
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    const FUNCTION: fw::MsgFunction = fw::MsgFunction::GspRunCpuSequencer;
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    type InitError = Error;
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    type Message = fw::RunCpuSequencer;
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    fn read(
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        msg: &Self::Message,
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        sbuffer: &mut SBufferIter<array::IntoIter<&[u8], 2>>,
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    ) -> Result<Self, Self::InitError> {
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        let cmd_data = sbuffer.flush_into_kvec(GFP_KERNEL)?;
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        Ok(GspSequence {
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            cmd_index: msg.cmd_index(),
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            cmd_data,
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        })
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    }
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}
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const CMD_SIZE: usize = size_of::<fw::SequencerBufferCmd>();
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/// GSP Sequencer Command types with payload data.
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/// Commands have an opcode and an opcode-dependent struct.
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#[allow(clippy::enum_variant_names)]
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pub(crate) enum GspSeqCmd {
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    RegWrite(fw::RegWritePayload),
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    RegModify(fw::RegModifyPayload),
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    RegPoll(fw::RegPollPayload),
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    DelayUs(fw::DelayUsPayload),
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    RegStore(fw::RegStorePayload),
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    CoreReset,
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    CoreStart,
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    CoreWaitForHalt,
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    CoreResume,
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}
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impl GspSeqCmd {
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    /// Creates a new `GspSeqCmd` from raw data returning the command and its size in bytes.
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    pub(crate) fn new(data: &[u8], dev: &device::Device) -> Result<(Self, usize)> {
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        let fw_cmd = fw::SequencerBufferCmd::from_bytes(data).ok_or(EINVAL)?;
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        let opcode_size = core::mem::size_of::<u32>();
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        let (cmd, size) = match fw_cmd.opcode()? {
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            fw::SeqBufOpcode::RegWrite => {
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                let payload = fw_cmd.reg_write_payload()?;
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                let size = opcode_size + size_of_val(&payload);
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                (GspSeqCmd::RegWrite(payload), size)
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            }
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            fw::SeqBufOpcode::RegModify => {
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                let payload = fw_cmd.reg_modify_payload()?;
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                let size = opcode_size + size_of_val(&payload);
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                (GspSeqCmd::RegModify(payload), size)
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            }
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            fw::SeqBufOpcode::RegPoll => {
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                let payload = fw_cmd.reg_poll_payload()?;
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                let size = opcode_size + size_of_val(&payload);
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                (GspSeqCmd::RegPoll(payload), size)
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            }
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            fw::SeqBufOpcode::DelayUs => {
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                let payload = fw_cmd.delay_us_payload()?;
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                let size = opcode_size + size_of_val(&payload);
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                (GspSeqCmd::DelayUs(payload), size)
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            }
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            fw::SeqBufOpcode::RegStore => {
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                let payload = fw_cmd.reg_store_payload()?;
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                let size = opcode_size + size_of_val(&payload);
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                (GspSeqCmd::RegStore(payload), size)
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            }
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            fw::SeqBufOpcode::CoreReset => (GspSeqCmd::CoreReset, opcode_size),
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            fw::SeqBufOpcode::CoreStart => (GspSeqCmd::CoreStart, opcode_size),
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            fw::SeqBufOpcode::CoreWaitForHalt => (GspSeqCmd::CoreWaitForHalt, opcode_size),
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            fw::SeqBufOpcode::CoreResume => (GspSeqCmd::CoreResume, opcode_size),
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        };
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        if data.len() < size {
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            dev_err!(dev, "Data is not enough for command\n");
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            return Err(EINVAL);
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        }
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        Ok((cmd, size))
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    }
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}
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/// GSP Sequencer for executing firmware commands during boot.
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pub(crate) struct GspSequencer<'a> {
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    /// Sequencer information with command data.
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    seq_info: GspSequence,
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    /// `Bar0` for register access.
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    bar: &'a Bar0,
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    /// SEC2 falcon for core operations.
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    sec2_falcon: &'a Falcon<Sec2>,
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    /// GSP falcon for core operations.
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    gsp_falcon: &'a Falcon<Gsp>,
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    /// LibOS DMA handle address.
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    libos_dma_handle: u64,
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    /// Bootloader application version.
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    bootloader_app_version: u32,
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    /// Device for logging.
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    dev: ARef<device::Device>,
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}
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/// Trait for running sequencer commands.
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pub(crate) trait GspSeqCmdRunner {
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    fn run(&self, sequencer: &GspSequencer<'_>) -> Result;
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}
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impl GspSeqCmdRunner for fw::RegWritePayload {
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    fn run(&self, sequencer: &GspSequencer<'_>) -> Result {
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        let addr = usize::from_safe_cast(self.addr());
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        sequencer.bar.try_write32(self.val(), addr)
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    }
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}
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impl GspSeqCmdRunner for fw::RegModifyPayload {
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    fn run(&self, sequencer: &GspSequencer<'_>) -> Result {
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        let addr = usize::from_safe_cast(self.addr());
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        sequencer.bar.try_read32(addr).and_then(|val| {
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            sequencer
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                .bar
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                .try_write32((val & !self.mask()) | self.val(), addr)
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        })
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    }
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}
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impl GspSeqCmdRunner for fw::RegPollPayload {
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    fn run(&self, sequencer: &GspSequencer<'_>) -> Result {
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        let addr = usize::from_safe_cast(self.addr());
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        // Default timeout to 4 seconds.
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        let timeout_us = if self.timeout() == 0 {
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            4_000_000
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        } else {
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            i64::from(self.timeout())
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        };
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        // First read.
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        sequencer.bar.try_read32(addr)?;
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        // Poll the requested register with requested timeout.
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        read_poll_timeout(
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            || sequencer.bar.try_read32(addr),
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            |current| (current & self.mask()) == self.val(),
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            Delta::ZERO,
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            Delta::from_micros(timeout_us),
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        )
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        .map(|_| ())
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    }
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}
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impl GspSeqCmdRunner for fw::DelayUsPayload {
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    fn run(&self, _sequencer: &GspSequencer<'_>) -> Result {
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        fsleep(Delta::from_micros(i64::from(self.val())));
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        Ok(())
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    }
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}
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impl GspSeqCmdRunner for fw::RegStorePayload {
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    fn run(&self, sequencer: &GspSequencer<'_>) -> Result {
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        let addr = usize::from_safe_cast(self.addr());
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        sequencer.bar.try_read32(addr).map(|_| ())
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    }
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}
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impl GspSeqCmdRunner for GspSeqCmd {
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    fn run(&self, seq: &GspSequencer<'_>) -> Result {
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        match self {
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            GspSeqCmd::RegWrite(cmd) => cmd.run(seq),
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            GspSeqCmd::RegModify(cmd) => cmd.run(seq),
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            GspSeqCmd::RegPoll(cmd) => cmd.run(seq),
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            GspSeqCmd::DelayUs(cmd) => cmd.run(seq),
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            GspSeqCmd::RegStore(cmd) => cmd.run(seq),
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            GspSeqCmd::CoreReset => {
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                seq.gsp_falcon.reset(seq.bar)?;
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                seq.gsp_falcon.dma_reset(seq.bar);
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                Ok(())
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            }
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            GspSeqCmd::CoreStart => {
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                seq.gsp_falcon.start(seq.bar)?;
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                Ok(())
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            }
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            GspSeqCmd::CoreWaitForHalt => {
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                seq.gsp_falcon.wait_till_halted(seq.bar)?;
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                Ok(())
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            }
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            GspSeqCmd::CoreResume => {
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                // At this point, 'SEC2-RTOS' has been loaded into SEC2 by the sequencer
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                // but neither SEC2-RTOS nor GSP-RM is running yet. This part of the
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                // sequencer will start both.
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                // Reset the GSP to prepare it for resuming.
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                seq.gsp_falcon.reset(seq.bar)?;
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                // Write the libOS DMA handle to GSP mailboxes.
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                seq.gsp_falcon.write_mailboxes(
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                    seq.bar,
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                    Some(seq.libos_dma_handle as u32),
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                    Some((seq.libos_dma_handle >> 32) as u32),
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                );
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                // Start the SEC2 falcon which will trigger GSP-RM to resume on the GSP.
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                seq.sec2_falcon.start(seq.bar)?;
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                // Poll until GSP-RM reload/resume has completed (up to 2 seconds).
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                seq.gsp_falcon
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                    .check_reload_completed(seq.bar, Delta::from_secs(2))?;
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                // Verify SEC2 completed successfully by checking its mailbox for errors.
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                let mbox0 = seq.sec2_falcon.read_mailbox0(seq.bar);
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                if mbox0 != 0 {
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                    dev_err!(seq.dev, "Sequencer: sec2 errors: {:?}\n", mbox0);
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                    return Err(EIO);
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                }
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                // Configure GSP with the bootloader version.
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                seq.gsp_falcon
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                    .write_os_version(seq.bar, seq.bootloader_app_version);
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                // Verify the GSP's RISC-V core is active indicating successful GSP boot.
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                if !seq.gsp_falcon.is_riscv_active(seq.bar) {
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                    dev_err!(seq.dev, "Sequencer: RISC-V core is not active\n");
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                    return Err(EIO);
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                }
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                Ok(())
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            }
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        }
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    }
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}
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/// Iterator over GSP sequencer commands.
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pub(crate) struct GspSeqIter<'a> {
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    /// Command data buffer.
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    cmd_data: &'a [u8],
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    /// Current position in the buffer.
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    current_offset: usize,
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    /// Total number of commands to process.
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    total_cmds: u32,
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    /// Number of commands processed so far.
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    cmds_processed: u32,
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    /// Device for logging.
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    dev: ARef<device::Device>,
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}
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impl<'a> Iterator for GspSeqIter<'a> {
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    type Item = Result<GspSeqCmd>;
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    fn next(&mut self) -> Option<Self::Item> {
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        // Stop if we've processed all commands or reached the end of data.
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        if self.cmds_processed >= self.total_cmds || self.current_offset >= self.cmd_data.len() {
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            return None;
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        }
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        // Check if we have enough data for opcode.
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        if self.current_offset + core::mem::size_of::<u32>() > self.cmd_data.len() {
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            return Some(Err(EIO));
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        }
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        let offset = self.current_offset;
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        // Handle command creation based on available data,
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        // zero-pad if necessary (since last command may not be full size).
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        let mut buffer = [0u8; CMD_SIZE];
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        let copy_len = if offset + CMD_SIZE <= self.cmd_data.len() {
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            CMD_SIZE
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        } else {
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            self.cmd_data.len() - offset
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        };
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        buffer[..copy_len].copy_from_slice(&self.cmd_data[offset..offset + copy_len]);
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        let cmd_result = GspSeqCmd::new(&buffer, &self.dev);
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        cmd_result.map_or_else(
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            |_err| {
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                dev_err!(self.dev, "Error parsing command at offset {}\n", offset);
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                None
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            },
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            |(cmd, size)| {
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                self.current_offset += size;
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                self.cmds_processed += 1;
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                Some(Ok(cmd))
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            },
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        )
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    }
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}
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impl<'a> GspSequencer<'a> {
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    fn iter(&self) -> GspSeqIter<'_> {
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        let cmd_data = &self.seq_info.cmd_data[..];
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        GspSeqIter {
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            cmd_data,
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            current_offset: 0,
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            total_cmds: self.seq_info.cmd_index,
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            cmds_processed: 0,
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            dev: self.dev.clone(),
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        }
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    }
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}
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/// Parameters for running the GSP sequencer.
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pub(crate) struct GspSequencerParams<'a> {
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    /// Bootloader application version.
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    pub(crate) bootloader_app_version: u32,
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    /// LibOS DMA handle address.
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    pub(crate) libos_dma_handle: u64,
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    /// GSP falcon for core operations.
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    pub(crate) gsp_falcon: &'a Falcon<Gsp>,
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    /// SEC2 falcon for core operations.
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    pub(crate) sec2_falcon: &'a Falcon<Sec2>,
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    /// Device for logging.
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    pub(crate) dev: ARef<device::Device>,
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    /// BAR0 for register access.
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    pub(crate) bar: &'a Bar0,
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}
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impl<'a> GspSequencer<'a> {
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    pub(crate) fn run(cmdq: &mut Cmdq, params: GspSequencerParams<'a>) -> Result {
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        let seq_info = loop {
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            match cmdq.receive_msg::<GspSequence>(Delta::from_secs(10)) {
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                Ok(seq_info) => break seq_info,
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                Err(ERANGE) => continue,
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                Err(e) => return Err(e),
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            }
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        };
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        let sequencer = GspSequencer {
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            seq_info,
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            bar: params.bar,
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            sec2_falcon: params.sec2_falcon,
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            gsp_falcon: params.gsp_falcon,
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            libos_dma_handle: params.libos_dma_handle,
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            bootloader_app_version: params.bootloader_app_version,
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            dev: params.dev,
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        };
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        dev_dbg!(sequencer.dev, "Running CPU Sequencer commands\n");
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        for cmd_result in sequencer.iter() {
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            match cmd_result {
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                Ok(cmd) => cmd.run(&sequencer)?,
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                Err(e) => {
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                    dev_err!(
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                        sequencer.dev,
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                        "Error running command at index {}\n",
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                        sequencer.seq_info.cmd_index
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                    );
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                    return Err(e);
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                }
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            }
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        }
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        dev_dbg!(
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            sequencer.dev,
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            "CPU Sequencer commands completed successfully\n"
401
        );
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        Ok(())
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    }
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}
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